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Register stack

register_stack

X86RegisterStack dataclass

Bases: RegisterStack

Available x86-specific registers.

Source code in xdsl/backend/x86/register_stack.py 
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@dataclass
class X86RegisterStack(RegisterStack):
    """
    Available x86-specific registers.
    """

    DEFAULT_ALLOCATABLE_REGISTERS = tuple(
        reversed(UNKNOWN.default_allocatable_registers())
    )

    @classmethod
    @override
    def default_allocatable_registers(cls):
        return cls.DEFAULT_ALLOCATABLE_REGISTERS

    @classmethod
    def get_for_arch(cls, arch: X86Arch, *, allow_infinite: bool = False):
        """
        Build a stack holding the registers this target can actually encode.

        Handing out the EVEX-only half of a vector bank on a VEX-only target
        produces assembly that target cannot run.
        """
        return cls.get(
            reversed(arch.default_allocatable_registers()),
            allow_infinite=allow_infinite,
        )

DEFAULT_ALLOCATABLE_REGISTERS = tuple(reversed(UNKNOWN.default_allocatable_registers())) class-attribute instance-attribute

__init__(allocatable_registers: defaultdict[str, set[int]] = (lambda: defaultdict(lambda: set[int]()))(), next_infinite_indices: defaultdict[str, int] = (lambda: defaultdict(lambda: 0))(), reserved_registers: defaultdict[str, defaultdict[int, int]] = (lambda: defaultdict(lambda: defaultdict[int, int](lambda: 0)))(), available_registers: defaultdict[str, list[int]] = (lambda: defaultdict(list[int]))(), allow_infinite: bool = False) -> None

default_allocatable_registers() classmethod

Source code in xdsl/backend/x86/register_stack.py 
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@classmethod
@override
def default_allocatable_registers(cls):
    return cls.DEFAULT_ALLOCATABLE_REGISTERS

get_for_arch(arch: X86Arch, *, allow_infinite: bool = False) classmethod

Build a stack holding the registers this target can actually encode.

Handing out the EVEX-only half of a vector bank on a VEX-only target produces assembly that target cannot run.

Source code in xdsl/backend/x86/register_stack.py 
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@classmethod
def get_for_arch(cls, arch: X86Arch, *, allow_infinite: bool = False):
    """
    Build a stack holding the registers this target can actually encode.

    Handing out the EVEX-only half of a vector bank on a VEX-only target
    produces assembly that target cannot run.
    """
    return cls.get(
        reversed(arch.default_allocatable_registers()),
        allow_infinite=allow_infinite,
    )