Index

riscv

This dialect contains a representation of the RISC-V ISA.

It currently models the 32-bit variant of the RISC-V instructions, but will be split into rv32 and rv64 to distinguish between the two variants.

RISCV = Dialect('riscv', [AddiOp, SltiOp, SltiuOp, AndiOp, OriOp, XoriOp, SlliOp, SrliOp, SraiOp, LuiOp, AuipcOp, MVOp, SeqzOp, SnezOp, ZextBOp, ZextWOp, SextWOp, AddOp, SltOp, SltuOp, AndOp, OrOp, XorOp, SllOp, SrlOp, SubOp, SraOp, NopOp, JalOp, JOp, JalrOp, ReturnOp, BeqOp, BneOp, BltOp, BgeOp, BltuOp, BgeuOp, LbOp, LbuOp, LhOp, LhuOp, LwOp, SbOp, ShOp, SwOp, CsrrwOp, CsrrsOp, CsrrcOp, CsrrwiOp, CsrrsiOp, CsrrciOp, MulOp, MulhOp, MulhsuOp, MulhuOp, DivOp, DivuOp, RemOp, RemuOp, LiOp, RolOp, RorOp, RemuwOp, SrliwOp, SraiwOp, AddwOp, SubwOp, SllwOp, SrlwOp, SrawOp, RemwOp, MulwOp, DivwOp, DivuwOp, CZeroEqzOp, CZeroNezOp, BclrOp, BextOp, BinvOp, BsetOp, RolwOp, RorwOp, AddUwOp, Sh1addOp, Sh2addOp, Sh3addOp, Sh1addUwOp, Sh2addUwOp, Sh3addUwOp, SextBOp, SextHOp, ZextHOp, AndnOp, OrnOp, XnorOp, MaxOp, MaxUOp, MinOp, MinUOp, BclrIOp, BextIOp, BsetIOp, BinvIOp, RoriOp, RoriwOp, SlliUwOp, EcallOp, LabelOp, DirectiveOp, AssemblySectionOp, EbreakOp, WfiOp, CustomAssemblyInstructionOp, CommentOp, GetRegisterOp, GetFloatRegisterOp, FMVOp, FMAddSOp, FMSubSOp, FNMSubSOp, FNMAddSOp, FAddSOp, FSubSOp, FMulSOp, FDivSOp, FSqrtSOp, FSgnJSOp, FSgnJNSOp, FSgnJXSOp, FMinSOp, FMaxSOp, FCvtWSOp, FCvtWuSOp, FMvXWOp, FeqSOp, FltSOp, FleSOp, FClassSOp, FCvtSWOp, FCvtSWuOp, FMvWXOp, FLwOp, FSwOp, FMAddDOp, FMSubDOp, FAddDOp, FSubDOp, FMulDOp, FDivDOp, FMinDOp, FMaxDOp, FCvtDWOp, FCvtDWuOp, FLdOp, FSdOp, FMvDOp, VFAddSOp, VFMulSOp, ParallelMovOp], [IntRegisterType, FloatRegisterType, LabelAttr, FastMathFlagsAttr]) module-attribute