Skip to content

Abstract ops

abstract_ops

AssemblyInstructionArg: TypeAlias = IntegerAttr | LabelAttr | SSAValue | RegisterType | str module-attribute

RISCVAsmOperation dataclass

Bases: IRDLOperation, OneLineAssemblyPrintable, ABC

Base class for operations that can be a part of RISC-V assembly printing.

Source code in xdsl/dialects/riscv/abstract_ops.py 
77
78
79
80
class RISCVAsmOperation(IRDLOperation, OneLineAssemblyPrintable, ABC):
    """
    Base class for operations that can be a part of RISC-V assembly printing.
    """

RISCVRegallocOperation dataclass

Bases: HasRegisterConstraints, IRDLOperation, ABC

Base class for operations that can take part in register allocation.

Source code in xdsl/dialects/riscv/abstract_ops.py 
83
84
85
86
87
88
89
90
91
92
class RISCVRegallocOperation(HasRegisterConstraints, IRDLOperation, ABC):
    """
    Base class for operations that can take part in register allocation.
    """

    def get_register_constraints(self) -> RegisterConstraints:
        # The default register constraints are that all operands are "in", and all
        # results are "out" registers.
        # If some registers are "inout" then this function must be overridden.
        return RegisterConstraints(self.operands, self.results, ())

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/riscv/abstract_ops.py 
88
89
90
91
92
def get_register_constraints(self) -> RegisterConstraints:
    # The default register constraints are that all operands are "in", and all
    # results are "out" registers.
    # If some registers are "inout" then this function must be overridden.
    return RegisterConstraints(self.operands, self.results, ())

RISCVCustomFormatOperation dataclass

Bases: IRDLOperation, ABC

Base class for RISC-V operations that specialize their custom format.

Source code in xdsl/dialects/riscv/abstract_ops.py 
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
class RISCVCustomFormatOperation(IRDLOperation, ABC):
    """
    Base class for RISC-V operations that specialize their custom format.
    """

    @classmethod
    def parse(cls, parser: Parser) -> Self:
        args = cls.parse_unresolved_operands(parser)
        custom_attributes = cls.custom_parse_attributes(parser)
        remaining_attributes = parser.parse_optional_attr_dict()
        # TODO ensure distinct keys for attributes
        attributes = custom_attributes | remaining_attributes
        regions = parser.parse_region_list()
        pos = parser.pos
        operand_types, result_types = cls.parse_op_type(parser)
        operands = parser.resolve_operands(args, operand_types, pos)
        return cls.create(
            operands=operands,
            result_types=result_types,
            attributes=attributes,
            regions=regions,
        )

    @classmethod
    def parse_unresolved_operands(cls, parser: Parser) -> list[UnresolvedOperand]:
        """
        Parse a list of comma separated unresolved operands.

        Notice that this method will consume trailing comma.
        """
        if operand := parser.parse_optional_unresolved_operand():
            operands = [operand]
            while parser.parse_optional_punctuation(",") and (
                operand := parser.parse_optional_unresolved_operand()
            ):
                operands.append(operand)
            return operands
        return []

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        """
        Parse attributes with custom syntax. Subclasses may override this method.
        """
        return parser.parse_optional_attr_dict()

    @classmethod
    def parse_op_type(
        cls, parser: Parser
    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
        parser.parse_punctuation(":")
        func_type = parser.parse_function_type()
        return func_type.inputs.data, func_type.outputs.data

    def print(self, printer: Printer) -> None:
        if self.operands:
            printer.print_string(" ")
            printer.print_list(self.operands, printer.print_operand)
        printed_attributes = self.custom_print_attributes(printer)
        unprinted_attributes = {
            name: attr
            for name, attr in self.attributes.items()
            if name not in printed_attributes
        }
        printer.print_op_attributes(unprinted_attributes)
        printer.print_regions(self.regions)
        self.print_op_type(printer)

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        """
        Print attributes with custom syntax. Return the names of the attributes printed. Subclasses may override this method.
        """
        printer.print_op_attributes(self.attributes)
        return self.attributes.keys()

    def print_op_type(self, printer: Printer) -> None:
        printer.print_string(" : ")
        printer.print_operation_type(self)

parse(parser: Parser) -> Self classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
@classmethod
def parse(cls, parser: Parser) -> Self:
    args = cls.parse_unresolved_operands(parser)
    custom_attributes = cls.custom_parse_attributes(parser)
    remaining_attributes = parser.parse_optional_attr_dict()
    # TODO ensure distinct keys for attributes
    attributes = custom_attributes | remaining_attributes
    regions = parser.parse_region_list()
    pos = parser.pos
    operand_types, result_types = cls.parse_op_type(parser)
    operands = parser.resolve_operands(args, operand_types, pos)
    return cls.create(
        operands=operands,
        result_types=result_types,
        attributes=attributes,
        regions=regions,
    )

parse_unresolved_operands(parser: Parser) -> list[UnresolvedOperand] classmethod

Parse a list of comma separated unresolved operands.

Notice that this method will consume trailing comma.

Source code in xdsl/dialects/riscv/abstract_ops.py 
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
@classmethod
def parse_unresolved_operands(cls, parser: Parser) -> list[UnresolvedOperand]:
    """
    Parse a list of comma separated unresolved operands.

    Notice that this method will consume trailing comma.
    """
    if operand := parser.parse_optional_unresolved_operand():
        operands = [operand]
        while parser.parse_optional_punctuation(",") and (
            operand := parser.parse_optional_unresolved_operand()
        ):
            operands.append(operand)
        return operands
    return []

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Parse attributes with custom syntax. Subclasses may override this method.

Source code in xdsl/dialects/riscv/abstract_ops.py 
134
135
136
137
138
139
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    """
    Parse attributes with custom syntax. Subclasses may override this method.
    """
    return parser.parse_optional_attr_dict()

parse_op_type(parser: Parser) -> tuple[Sequence[Attribute], Sequence[Attribute]] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
141
142
143
144
145
146
147
@classmethod
def parse_op_type(
    cls, parser: Parser
) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
    parser.parse_punctuation(":")
    func_type = parser.parse_function_type()
    return func_type.inputs.data, func_type.outputs.data

print(printer: Printer) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
149
150
151
152
153
154
155
156
157
158
159
160
161
def print(self, printer: Printer) -> None:
    if self.operands:
        printer.print_string(" ")
        printer.print_list(self.operands, printer.print_operand)
    printed_attributes = self.custom_print_attributes(printer)
    unprinted_attributes = {
        name: attr
        for name, attr in self.attributes.items()
        if name not in printed_attributes
    }
    printer.print_op_attributes(unprinted_attributes)
    printer.print_regions(self.regions)
    self.print_op_type(printer)

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Print attributes with custom syntax. Return the names of the attributes printed. Subclasses may override this method.

Source code in xdsl/dialects/riscv/abstract_ops.py 
163
164
165
166
167
168
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    """
    Print attributes with custom syntax. Return the names of the attributes printed. Subclasses may override this method.
    """
    printer.print_op_attributes(self.attributes)
    return self.attributes.keys()

print_op_type(printer: Printer) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
170
171
172
def print_op_type(self, printer: Printer) -> None:
    printer.print_string(" : ")
    printer.print_operation_type(self)

RISCVInstruction dataclass

Bases: RISCVAsmOperation, RISCVRegallocOperation, ABC

Base class for operations that can be a part of RISC-V assembly printing. Must represent an instruction in the RISC-V instruction set, and have the following format:

name arg0, arg1, arg2 # comment

The name of the operation will be used as the RISC-V assembly instruction name.

Source code in xdsl/dialects/riscv/abstract_ops.py 
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
class RISCVInstruction(RISCVAsmOperation, RISCVRegallocOperation, ABC):
    """
    Base class for operations that can be a part of RISC-V assembly printing. Must
    represent an instruction in the RISC-V instruction set, and have the following format:

    name arg0, arg1, arg2           # comment

    The name of the operation will be used as the RISC-V assembly instruction name.
    """

    comment = opt_attr_def(StringAttr)
    """
    An optional comment that will be printed along with the instruction.
    """

    @abstractmethod
    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        """
        The arguments to the instruction, in the order they should be printed in the
        assembly.
        """
        raise NotImplementedError()

    def assembly_instruction_name(self) -> str:
        """
        By default, the name of the instruction is the same as the name of the operation.
        """

        return Dialect.split_name(self.name)[1]

    def assembly_line(self) -> str | None:
        # default assembly code generator
        instruction_name = self.assembly_instruction_name()
        arg_str = ", ".join(
            assembly_arg_str(arg)
            for arg in self.assembly_line_args()
            if arg is not None
        )
        return AssemblyPrinter.assembly_line(instruction_name, arg_str, self.comment)

comment = opt_attr_def(StringAttr) class-attribute instance-attribute

An optional comment that will be printed along with the instruction.

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...] abstractmethod

The arguments to the instruction, in the order they should be printed in the assembly.

Source code in xdsl/dialects/riscv/abstract_ops.py 
195
196
197
198
199
200
201
@abstractmethod
def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    """
    The arguments to the instruction, in the order they should be printed in the
    assembly.
    """
    raise NotImplementedError()

assembly_instruction_name() -> str

By default, the name of the instruction is the same as the name of the operation.

Source code in xdsl/dialects/riscv/abstract_ops.py 
203
204
205
206
207
208
def assembly_instruction_name(self) -> str:
    """
    By default, the name of the instruction is the same as the name of the operation.
    """

    return Dialect.split_name(self.name)[1]

assembly_line() -> str | None

Source code in xdsl/dialects/riscv/abstract_ops.py 
210
211
212
213
214
215
216
217
218
def assembly_line(self) -> str | None:
    # default assembly code generator
    instruction_name = self.assembly_instruction_name()
    arg_str = ", ".join(
        assembly_arg_str(arg)
        for arg in self.assembly_line_args()
        if arg is not None
    )
    return AssemblyPrinter.assembly_line(instruction_name, arg_str, self.comment)

RISCVAsmTarget dataclass

Bases: Target

Source code in xdsl/dialects/riscv/abstract_ops.py 
250
251
252
253
254
255
@dataclass(frozen=True)
class RISCVAsmTarget(Target):
    name = "riscv-asm"

    def emit(self, ctx: Context, module: ModuleOp, output: IO[str]) -> None:
        print_assembly(module, output)

name = 'riscv-asm' class-attribute instance-attribute

__init__() -> None

emit(ctx: Context, module: ModuleOp, output: IO[str]) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
254
255
def emit(self, ctx: Context, module: ModuleOp, output: IO[str]) -> None:
    print_assembly(module, output)

RdRsRsOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC, Generic[RDInvT, RS1InvT, RS2InvT]

A base class for RISC-V operations that have one destination register, and two source registers.

This is called R-Type in the RISC-V specification.

Source code in xdsl/dialects/riscv/abstract_ops.py 
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
class RdRsRsOperation(
    RISCVCustomFormatOperation, RISCVInstruction, ABC, Generic[RDInvT, RS1InvT, RS2InvT]
):
    """
    A base class for RISC-V operations that have one destination register, and two source
    registers.

    This is called R-Type in the RISC-V specification.
    """

    rd: OpResult[RDInvT] = result_def(RDInvT)
    rs1 = operand_def(RS1InvT)
    rs2 = operand_def(RS2InvT)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        *,
        rd: RDInvT = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "comment": comment,
            },
            result_types=[rd],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.rs2

rd: OpResult[RDInvT] = result_def(RDInvT) class-attribute instance-attribute

rs1 = operand_def(RS1InvT) class-attribute instance-attribute

rs2 = operand_def(RS2InvT) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, *, rd: RDInvT = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    *,
    rd: RDInvT = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "comment": comment,
        },
        result_types=[rd],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
296
297
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.rs2

RdRsRsIntegerOperation

Bases: RdRsRsOperation[IntRegisterType, RS1InvT, RS2InvT], ABC, Generic[RS1InvT, RS2InvT]

Source code in xdsl/dialects/riscv/abstract_ops.py 
300
301
302
303
304
305
306
307
308
309
310
311
class RdRsRsIntegerOperation(
    RdRsRsOperation[IntRegisterType, RS1InvT, RS2InvT], ABC, Generic[RS1InvT, RS2InvT]
):
    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        super().__init__(rs1, rs2, rd=rd, comment=comment)

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
303
304
305
306
307
308
309
310
311
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    super().__init__(rs1, rs2, rd=rd, comment=comment)

RdRsRsFloatOperation

Bases: RdRsRsOperation[FloatRegisterType, RS1InvT, RS2InvT], ABC, Generic[RS1InvT, RS2InvT]

Source code in xdsl/dialects/riscv/abstract_ops.py 
314
315
316
317
318
319
320
321
322
323
324
325
class RdRsRsFloatOperation(
    RdRsRsOperation[FloatRegisterType, RS1InvT, RS2InvT], ABC, Generic[RS1InvT, RS2InvT]
):
    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        *,
        rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
        comment: str | StringAttr | None = None,
    ):
        super().__init__(rs1, rs2, rd=rd, comment=comment)

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, *, rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
317
318
319
320
321
322
323
324
325
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    *,
    rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
    comment: str | StringAttr | None = None,
):
    super().__init__(rs1, rs2, rd=rd, comment=comment)

RsRsImmFloatOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RV32F operations that have two source registers (one integer and one floating-point) and an immediate.

Source code in xdsl/dialects/riscv/abstract_ops.py 
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
class RsRsImmFloatOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RV32F operations that have two source registers
    (one integer and one floating-point) and an immediate.
    """

    rs1 = operand_def(IntRegisterType)
    rs2 = operand_def(FloatRegisterType)
    immediate = attr_def(IntegerAttr[I12])

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        immediate: int | IntegerAttr[I12] | str | LabelAttr,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, i12)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rs1, self.rs2, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, i12)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        return {"immediate"}

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

rs2 = operand_def(FloatRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[I12]) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, immediate: int | IntegerAttr[I12] | str | LabelAttr, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    immediate: int | IntegerAttr[I12] | str | LabelAttr,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, i12)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
361
362
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rs1, self.rs2, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
364
365
366
367
368
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, i12)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
370
371
372
373
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    return {"immediate"}

RdRsImmFloatOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RV32Foperations that have one floating-point destination register, one source register and one immediate operand.

Source code in xdsl/dialects/riscv/abstract_ops.py 
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
class RdRsImmFloatOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RV32Foperations that have one floating-point
    destination register, one source register and
    one immediate operand.
    """

    rd = result_def(FloatRegisterType)
    rs1 = operand_def(IntRegisterType)
    immediate = attr_def(IntegerAttr[I12] | LabelAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        immediate: int | IntegerAttr[I12] | str | LabelAttr,
        *,
        rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, i12)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)

        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1],
            result_types=[rd],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, i12)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        return {"immediate"}

rd = result_def(FloatRegisterType) class-attribute instance-attribute

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[I12] | LabelAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, immediate: int | IntegerAttr[I12] | str | LabelAttr, *, rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
def __init__(
    self,
    rs1: Operation | SSAValue,
    immediate: int | IntegerAttr[I12] | str | LabelAttr,
    *,
    rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, i12)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)

    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1],
        result_types=[rd],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
411
412
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
414
415
416
417
418
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, i12)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
420
421
422
423
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    return {"immediate"}

RdRsRsRsFloatOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RV32F operations that take three floating-point input registers and a destination register, e.g: fused-multiply-add (FMA) instructions.

Source code in xdsl/dialects/riscv/abstract_ops.py 
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
class RdRsRsRsFloatOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RV32F operations that take three
    floating-point input registers and a destination register,
    e.g: fused-multiply-add (FMA) instructions.
    """

    rd = result_def(FloatRegisterType)
    rs1 = operand_def(FloatRegisterType)
    rs2 = operand_def(FloatRegisterType)
    rs3 = operand_def(FloatRegisterType)

    traits = traits_def(RegisterAllocatedMemoryEffect())

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        rs3: Operation | SSAValue,
        *,
        rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2, rs3],
            attributes={
                "comment": comment,
            },
            result_types=[rd],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.rs2, self.rs3

rd = result_def(FloatRegisterType) class-attribute instance-attribute

rs1 = operand_def(FloatRegisterType) class-attribute instance-attribute

rs2 = operand_def(FloatRegisterType) class-attribute instance-attribute

rs3 = operand_def(FloatRegisterType) class-attribute instance-attribute

traits = traits_def(RegisterAllocatedMemoryEffect()) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, rs3: Operation | SSAValue, *, rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    rs3: Operation | SSAValue,
    *,
    rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2, rs3],
        attributes={
            "comment": comment,
        },
        result_types=[rd],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
460
461
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.rs2, self.rs3

RdRsRsFloatFloatIntegerOperationWithFastMath

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have two source floating-point registers with an integer destination register, and can be annotated with fastmath flags.

This is called R-Type in the RISC-V specification.

Source code in xdsl/dialects/riscv/abstract_ops.py 
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
class RdRsRsFloatFloatIntegerOperationWithFastMath(
    RISCVCustomFormatOperation, RISCVInstruction, ABC
):
    """
    A base class for RISC-V operations that have two source floating-point
    registers with an integer destination register, and can be annotated with fastmath flags.

    This is called R-Type in the RISC-V specification.
    """

    rd = result_def(IntRegisterType)
    rs1 = operand_def(FloatRegisterType)
    rs2 = operand_def(FloatRegisterType)
    fastmath = attr_def(FastMathFlagsAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        fastmath: FastMathFlagsAttr = FastMathFlagsAttr("none"),
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "comment": comment,
                "fastmath": fastmath,
            },
            result_types=[rd],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.rs2

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        fast = FastMathFlagsAttr("none")
        if parser.parse_optional_keyword("fastmath") is not None:
            fast = FastMathFlagsAttr(FastMathFlagsAttr.parse_parameter(parser))
        attributes["fastmath"] = fast
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        if self.fastmath != FastMathFlagsAttr("none"):
            printer.print_string(" fastmath")
            self.fastmath.print_parameter(printer)
        return {"fastmath"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

rs1 = operand_def(FloatRegisterType) class-attribute instance-attribute

rs2 = operand_def(FloatRegisterType) class-attribute instance-attribute

fastmath = attr_def(FastMathFlagsAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, fastmath: FastMathFlagsAttr = FastMathFlagsAttr('none'), comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    fastmath: FastMathFlagsAttr = FastMathFlagsAttr("none"),
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "comment": comment,
            "fastmath": fastmath,
        },
        result_types=[rd],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
500
501
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.rs2

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
503
504
505
506
507
508
509
510
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    fast = FastMathFlagsAttr("none")
    if parser.parse_optional_keyword("fastmath") is not None:
        fast = FastMathFlagsAttr(FastMathFlagsAttr.parse_parameter(parser))
    attributes["fastmath"] = fast
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
512
513
514
515
516
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    if self.fastmath != FastMathFlagsAttr("none"):
        printer.print_string(" fastmath")
        self.fastmath.print_parameter(printer)
    return {"fastmath"}

RdRsRsFloatOperationWithFastMath

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have one destination floating-point register, and two source floating-point registers and can be annotated with fastmath flags.

This is called R-Type in the RISC-V specification.

Source code in xdsl/dialects/riscv/abstract_ops.py 
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
class RdRsRsFloatOperationWithFastMath(
    RISCVCustomFormatOperation, RISCVInstruction, ABC
):
    """
    A base class for RISC-V operations that have one destination floating-point register,
    and two source floating-point registers and can be annotated with fastmath flags.

    This is called R-Type in the RISC-V specification.
    """

    rd = result_def(FloatRegisterType)
    rs1 = operand_def(FloatRegisterType)
    rs2 = operand_def(FloatRegisterType)
    fastmath = opt_attr_def(FastMathFlagsAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        *,
        rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
        fastmath: FastMathFlagsAttr | None = None,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "fastmath": fastmath,
                "comment": comment,
            },
            result_types=[rd],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.rs2

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        flags = FastMathFlagsAttr("none")
        if parser.parse_optional_keyword("fastmath") is not None:
            flags = FastMathFlagsAttr(FastMathFlagsAttr.parse_parameter(parser))
        attributes["fastmath"] = flags
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        if self.fastmath is not None and self.fastmath != FastMathFlagsAttr("none"):
            printer.print_string(" fastmath")
            self.fastmath.print_parameter(printer)
        return {"fastmath"}

rd = result_def(FloatRegisterType) class-attribute instance-attribute

rs1 = operand_def(FloatRegisterType) class-attribute instance-attribute

rs2 = operand_def(FloatRegisterType) class-attribute instance-attribute

fastmath = opt_attr_def(FastMathFlagsAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, *, rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT, fastmath: FastMathFlagsAttr | None = None, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    *,
    rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
    fastmath: FastMathFlagsAttr | None = None,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "fastmath": fastmath,
            "comment": comment,
        },
        result_types=[rd],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
555
556
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.rs2

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
558
559
560
561
562
563
564
565
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    flags = FastMathFlagsAttr("none")
    if parser.parse_optional_keyword("fastmath") is not None:
        flags = FastMathFlagsAttr(FastMathFlagsAttr.parse_parameter(parser))
    attributes["fastmath"] = flags
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
567
568
569
570
571
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    if self.fastmath is not None and self.fastmath != FastMathFlagsAttr("none"):
        printer.print_string(" fastmath")
        self.fastmath.print_parameter(printer)
    return {"fastmath"}

RdImmIntegerOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have one destination register, and one immediate operand (e.g. U-Type and J-Type instructions in the RISC-V spec).

Source code in xdsl/dialects/riscv/abstract_ops.py 
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
class RdImmIntegerOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have one destination register, and one
    immediate operand (e.g. U-Type and J-Type instructions in the RISC-V spec).
    """

    rd = result_def(IntRegisterType)
    immediate = attr_def(IntegerAttr[I20] | LabelAttr)

    def __init__(
        self,
        immediate: int | IntegerAttr | str | LabelAttr,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, i20)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            result_types=[rd],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, i20)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(" ")
        print_immediate_value(printer, self.immediate)
        return {"immediate"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[I20] | LabelAttr) class-attribute instance-attribute

__init__(immediate: int | IntegerAttr | str | LabelAttr, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
def __init__(
    self,
    immediate: int | IntegerAttr | str | LabelAttr,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, i20)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        result_types=[rd],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
605
606
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
608
609
610
611
612
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, i20)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
614
615
616
617
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(" ")
    print_immediate_value(printer, self.immediate)
    return {"immediate"}

RdImmJumpOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

In the RISC-V spec, this is the same as RdImmOperation. For jumps, the rd register is neither an operand, because the stored value is overwritten, nor a result value, because the value in rd is not defined after the jump back. So the rd makes the most sense as an attribute.

Source code in xdsl/dialects/riscv/abstract_ops.py 
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
class RdImmJumpOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    In the RISC-V spec, this is the same as `RdImmOperation`. For jumps, the `rd` register
    is neither an operand, because the stored value is overwritten, nor a result value,
    because the value in `rd` is not defined after the jump back. So the `rd` makes the
    most sense as an attribute.
    """

    rd = opt_attr_def(IntRegisterType)
    """
    The rd register here is not a register storing the result, rather the register where
    the program counter is stored before jumping.
    """
    immediate = attr_def(IntegerAttr[SI20] | LabelAttr)

    def __init__(
        self,
        immediate: int | IntegerAttr[SI20] | str | LabelAttr,
        *,
        rd: IntRegisterType | None = None,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si20)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            attributes={
                "immediate": immediate,
                "rd": rd,
                "comment": comment,
            }
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return self.rd, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, si20)
        if parser.parse_optional_punctuation(","):
            attributes["rd"] = parser.parse_attribute()
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(" ")
        print_immediate_value(printer, self.immediate)
        if self.rd is not None:
            printer.print_string(", ")
            printer.print_attribute(self.rd)
        return {"immediate", "rd"}

    def print_op_type(self, printer: Printer) -> None:
        return

    @classmethod
    def parse_op_type(
        cls, parser: Parser
    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
        return (), ()

rd = opt_attr_def(IntRegisterType) class-attribute instance-attribute

The rd register here is not a register storing the result, rather the register where the program counter is stored before jumping.

immediate = attr_def(IntegerAttr[SI20] | LabelAttr) class-attribute instance-attribute

__init__(immediate: int | IntegerAttr[SI20] | str | LabelAttr, *, rd: IntRegisterType | None = None, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
def __init__(
    self,
    immediate: int | IntegerAttr[SI20] | str | LabelAttr,
    *,
    rd: IntRegisterType | None = None,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si20)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        attributes={
            "immediate": immediate,
            "rd": rd,
            "comment": comment,
        }
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
656
657
def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return self.rd, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
659
660
661
662
663
664
665
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, si20)
    if parser.parse_optional_punctuation(","):
        attributes["rd"] = parser.parse_attribute()
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
667
668
669
670
671
672
673
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(" ")
    print_immediate_value(printer, self.immediate)
    if self.rd is not None:
        printer.print_string(", ")
        printer.print_attribute(self.rd)
    return {"immediate", "rd"}

print_op_type(printer: Printer) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
675
676
def print_op_type(self, printer: Printer) -> None:
    return

parse_op_type(parser: Parser) -> tuple[Sequence[Attribute], Sequence[Attribute]] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
678
679
680
681
682
@classmethod
def parse_op_type(
    cls, parser: Parser
) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
    return (), ()

RdRsImmIntegerOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have one destination register, one source register and one immediate operand.

This is called I-Type in the RISC-V specification.

Source code in xdsl/dialects/riscv/abstract_ops.py 
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
class RdRsImmIntegerOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have one destination register, one source
    register and one immediate operand.

    This is called I-Type in the RISC-V specification.
    """

    rd = result_def(IntRegisterType)
    rs1 = operand_def(IntRegisterType)
    immediate = attr_def(IntegerAttr[SI12] | LabelAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        immediate: int | IntegerAttr[SI12] | str | LabelAttr,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si12)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)

        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1],
            result_types=[rd],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, si12)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        return {"immediate"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI12] | LabelAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, immediate: int | IntegerAttr[SI12] | str | LabelAttr, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
def __init__(
    self,
    rs1: Operation | SSAValue,
    immediate: int | IntegerAttr[SI12] | str | LabelAttr,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si12)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)

    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1],
        result_types=[rd],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
721
722
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
724
725
726
727
728
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, si12)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
730
731
732
733
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    return {"immediate"}

ImmShiftOpHasCanonicalizationPatternsTrait dataclass

Bases: HasCanonicalizationPatternsTrait

Source code in xdsl/dialects/riscv/abstract_ops.py 
736
737
738
739
740
741
742
743
744
class ImmShiftOpHasCanonicalizationPatternsTrait(HasCanonicalizationPatternsTrait):
    @classmethod
    def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
        from xdsl.transforms.canonicalization_patterns.riscv import (
            ShiftbyZero,
            ShiftConstantFolding,
        )

        return (ShiftbyZero(), ShiftConstantFolding())

get_canonicalization_patterns() -> tuple[RewritePattern, ...] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
737
738
739
740
741
742
743
744
@classmethod
def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
    from xdsl.transforms.canonicalization_patterns.riscv import (
        ShiftbyZero,
        ShiftConstantFolding,
    )

    return (ShiftbyZero(), ShiftConstantFolding())

RdRsImmShiftOperation

Bases: RISCVInstruction, ABC

A base class for RISC-V operations that have one destination register, one source register and one immediate operand.

This is called I-Type in the RISC-V specification.

Shifts by a constant are encoded as a specialization of the I-type format. The shift amount is encoded in the lower 5 bits of the I-immediate field for RV32

For RV32I, SLLI, SRLI, and SRAI generate an illegal instruction exception if imm[5] 6 != 0 but the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I.

Source code in xdsl/dialects/riscv/abstract_ops.py 
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
class RdRsImmShiftOperation(RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have one destination register, one source
    register and one immediate operand.

    This is called I-Type in the RISC-V specification.

    Shifts by a constant are encoded as a specialization of the I-type format.
    The shift amount is encoded in the lower 5 bits of the I-immediate field for RV32

    For RV32I, SLLI, SRLI, and SRAI generate an illegal instruction exception if
    imm[5] 6 != 0 but the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I.
    """

    rd = result_def(IntRegisterType)
    rs1 = operand_def(IntRegisterType)
    immediate = attr_def(IntegerAttr[UI5])
    traits = traits_def(ImmShiftOpHasCanonicalizationPatternsTrait())

    assembly_format = (
        "$rs1 `,` $immediate attr-dict `:` `(` type($rs1) `)` `->` type($rd)"
    )

    def __init__(
        self,
        rs1: Operation | SSAValue,
        immediate: int | IntegerAttr[UI5],
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, ui5)

        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1],
            result_types=[rd],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.immediate

    @abstractmethod
    def py_operation(self, rs1: IntegerAttr[I32]) -> IntegerAttr[I32]:
        """
        Performs a python function corresponding to this operation.

        If `i := py_operation(rs1)` is an IntegerAttr[I32], then this operation can be
        canonicalized to a constant with value `i` when the inputs are constants
        with values `rs1`. The immediate value is retrieved from the `immediate` attribute of the operation.
        """

        raise NotImplementedError(
            "RdRsImmShiftOperation py_operation is not yet implemented"
        )

rd = result_def(IntRegisterType) class-attribute instance-attribute

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[UI5]) class-attribute instance-attribute

traits = traits_def(ImmShiftOpHasCanonicalizationPatternsTrait()) class-attribute instance-attribute

assembly_format = '$rs1 `,` $immediate attr-dict `:` `(` type($rs1) `)` `->` type($rd)' class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, immediate: int | IntegerAttr[UI5], *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
def __init__(
    self,
    rs1: Operation | SSAValue,
    immediate: int | IntegerAttr[UI5],
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, ui5)

    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1],
        result_types=[rd],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
792
793
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.immediate

py_operation(rs1: IntegerAttr[I32]) -> IntegerAttr[I32] abstractmethod

Performs a python function corresponding to this operation.

If i := py_operation(rs1) is an IntegerAttr[I32], then this operation can be canonicalized to a constant with value i when the inputs are constants with values rs1. The immediate value is retrieved from the immediate attribute of the operation.

Source code in xdsl/dialects/riscv/abstract_ops.py 
795
796
797
798
799
800
801
802
803
804
805
806
807
@abstractmethod
def py_operation(self, rs1: IntegerAttr[I32]) -> IntegerAttr[I32]:
    """
    Performs a python function corresponding to this operation.

    If `i := py_operation(rs1)` is an IntegerAttr[I32], then this operation can be
    canonicalized to a constant with value `i` when the inputs are constants
    with values `rs1`. The immediate value is retrieved from the `immediate` attribute of the operation.
    """

    raise NotImplementedError(
        "RdRsImmShiftOperation py_operation is not yet implemented"
    )

RdRsImmBitManipOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have one destination register, one source register and one immediate operand.

These operations are from the Zba, Zbb, and Zbs extensions.

The immediate value is encoded in the lower 5 bits of the immediate field for RV32 and the lower 6 bits for RV64.

See external documentation.

Source code in xdsl/dialects/riscv/abstract_ops.py 
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
class RdRsImmBitManipOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have one destination register, one source
    register and one immediate operand.

    These operations are from the Zba, Zbb, and Zbs extensions.

    The immediate value is encoded in the lower 5 bits of the immediate field for RV32
    and the lower 6 bits for RV64.

    See external [documentation](https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#).
    """

    rd = result_def(IntRegisterType)
    rs1 = operand_def(IntRegisterType)
    immediate = attr_def(IntegerAttr[UI5] | LabelAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        immediate: int | IntegerAttr[UI5] | str | LabelAttr,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, ui5)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)

        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1],
            result_types=[rd],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs1, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, ui5)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        return {"immediate"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[UI5] | LabelAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, immediate: int | IntegerAttr[UI5] | str | LabelAttr, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
def __init__(
    self,
    rs1: Operation | SSAValue,
    immediate: int | IntegerAttr[UI5] | str | LabelAttr,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, ui5)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)

    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1],
        result_types=[rd],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
851
852
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs1, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
854
855
856
857
858
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, ui5)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
860
861
862
863
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    return {"immediate"}

RdRsImmJumpOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have one destination register, one source register and one immediate operand.

This is called I-Type in the RISC-V specification.

In the RISC-V spec, this is the same as RdRsImmOperation. For jumps, the rd register is neither an operand, because the stored value is overwritten, nor a result value, because the value in rd is not defined after the jump back. So the rd makes the most sense as an attribute.

Source code in xdsl/dialects/riscv/abstract_ops.py 
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
class RdRsImmJumpOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have one destination register, one source
    register and one immediate operand.

    This is called I-Type in the RISC-V specification.

    In the RISC-V spec, this is the same as `RdRsImmOperation`. For jumps, the `rd` register
    is neither an operand, because the stored value is overwritten, nor a result value,
    because the value in `rd` is not defined after the jump back. So the `rd` makes the
    most sense as an attribute.
    """

    rs1 = operand_def(IntRegisterType)
    rd = opt_attr_def(IntRegisterType)
    """
    The rd register here is not a register storing the result, rather the register where
    the program counter is stored before jumping.
    """
    immediate = attr_def(IntegerAttr[SI12] | LabelAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        immediate: int | IntegerAttr[SI12] | str | LabelAttr,
        *,
        rd: IntRegisterType | None = None,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si12)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)

        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1],
            attributes={
                "immediate": immediate,
                "rd": rd,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return self.rd, self.rs1, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, si12)
        if parser.parse_optional_punctuation(","):
            attributes["rd"] = parser.parse_attribute()
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        if self.rd is not None:
            printer.print_string(", ")
            printer.print_attribute(self.rd)
        return {"immediate", "rd"}

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

rd = opt_attr_def(IntRegisterType) class-attribute instance-attribute

The rd register here is not a register storing the result, rather the register where the program counter is stored before jumping.

immediate = attr_def(IntegerAttr[SI12] | LabelAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, immediate: int | IntegerAttr[SI12] | str | LabelAttr, *, rd: IntRegisterType | None = None, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
def __init__(
    self,
    rs1: Operation | SSAValue,
    immediate: int | IntegerAttr[SI12] | str | LabelAttr,
    *,
    rd: IntRegisterType | None = None,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si12)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)

    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1],
        attributes={
            "immediate": immediate,
            "rd": rd,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
912
913
def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return self.rd, self.rs1, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
915
916
917
918
919
920
921
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, si12)
    if parser.parse_optional_punctuation(","):
        attributes["rd"] = parser.parse_attribute()
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
923
924
925
926
927
928
929
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    if self.rd is not None:
        printer.print_string(", ")
        printer.print_attribute(self.rd)
    return {"immediate", "rd"}

RdRsOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC, Generic[RDInvT, RSInvT]

A base class for RISC-V pseudo-instructions that have one destination register and one source register.

Source code in xdsl/dialects/riscv/abstract_ops.py 
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
class RdRsOperation(
    RISCVCustomFormatOperation, RISCVInstruction, ABC, Generic[RDInvT, RSInvT]
):
    """
    A base class for RISC-V pseudo-instructions that have one destination register and one
    source register.
    """

    rd = result_def(RDInvT)
    rs = operand_def(RSInvT)

    def __init__(
        self,
        rs: Operation | SSAValue,
        *,
        rd: RDInvT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs],
            result_types=[rd],
            attributes={"comment": comment},
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.rs

rd = result_def(RDInvT) class-attribute instance-attribute

rs = operand_def(RSInvT) class-attribute instance-attribute

__init__(rs: Operation | SSAValue, *, rd: RDInvT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
943
944
945
946
947
948
949
950
951
952
953
954
955
956
def __init__(
    self,
    rs: Operation | SSAValue,
    *,
    rd: RDInvT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs],
        result_types=[rd],
        attributes={"comment": comment},
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
958
959
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.rs

RdRsIntegerOperation

Bases: RdRsOperation[IntRegisterType, RSInvT], ABC, Generic[RSInvT]

Source code in xdsl/dialects/riscv/abstract_ops.py 
962
963
964
965
966
967
968
969
970
971
972
class RdRsIntegerOperation(
    RdRsOperation[IntRegisterType, RSInvT], ABC, Generic[RSInvT]
):
    def __init__(
        self,
        rs: Operation | SSAValue,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        super().__init__(rs, rd=rd, comment=comment)

__init__(rs: Operation | SSAValue, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
965
966
967
968
969
970
971
972
def __init__(
    self,
    rs: Operation | SSAValue,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    super().__init__(rs, rd=rd, comment=comment)

RdRsFloatOperation

Bases: RdRsOperation[FloatRegisterType, RSInvT], ABC, Generic[RSInvT]

Source code in xdsl/dialects/riscv/abstract_ops.py 
975
976
977
978
979
980
981
982
983
984
985
class RdRsFloatOperation(
    RdRsOperation[FloatRegisterType, RSInvT], ABC, Generic[RSInvT]
):
    def __init__(
        self,
        rs: Operation | SSAValue,
        *,
        rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
        comment: str | StringAttr | None = None,
    ):
        super().__init__(rs, rd=rd, comment=comment)

__init__(rs: Operation | SSAValue, *, rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
978
979
980
981
982
983
984
985
def __init__(
    self,
    rs: Operation | SSAValue,
    *,
    rd: FloatRegisterType = Registers.UNALLOCATED_FLOAT,
    comment: str | StringAttr | None = None,
):
    super().__init__(rs, rd=rd, comment=comment)

RsRsOffIntegerOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have one source register and a destination register, and an offset.

This is called B-Type in the RISC-V specification.

Source code in xdsl/dialects/riscv/abstract_ops.py 
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
class RsRsOffIntegerOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have one source register and a destination
    register, and an offset.

    This is called B-Type in the RISC-V specification.
    """

    rs1 = operand_def(IntRegisterType)
    rs2 = operand_def(IntRegisterType)
    offset = attr_def(IntegerAttr[SI12] | LabelAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        offset: int | IntegerAttr[SI12] | LabelAttr,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(offset, int):
            offset = IntegerAttr(offset, si12)
        if isinstance(offset, str):
            offset = LabelAttr(offset)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "offset": offset,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rs1, self.rs2, self.offset

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["offset"] = parse_immediate_value(parser, si12)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.offset)
        return {"offset"}

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

rs2 = operand_def(IntRegisterType) class-attribute instance-attribute

offset = attr_def(IntegerAttr[SI12] | LabelAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, offset: int | IntegerAttr[SI12] | LabelAttr, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    offset: int | IntegerAttr[SI12] | LabelAttr,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(offset, int):
        offset = IntegerAttr(offset, si12)
    if isinstance(offset, str):
        offset = LabelAttr(offset)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "offset": offset,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1023
1024
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rs1, self.rs2, self.offset

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1026
1027
1028
1029
1030
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["offset"] = parse_immediate_value(parser, si12)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1032
1033
1034
1035
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.offset)
    return {"offset"}

RsRsImmIntegerOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have two source registers and an immediate.

This is called S-Type in the RISC-V specification.

Source code in xdsl/dialects/riscv/abstract_ops.py 
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
class RsRsImmIntegerOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have two source registers and an
    immediate.

    This is called S-Type in the RISC-V specification.
    """

    rs1 = operand_def(IntRegisterType)
    rs2 = operand_def(IntRegisterType)
    immediate = attr_def(IntegerAttr[SI12])

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        immediate: int | IntegerAttr[SI12] | str | LabelAttr,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si12)
        elif isinstance(immediate, str):
            immediate = LabelAttr(immediate)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rs1, self.rs2, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["immediate"] = parse_immediate_value(parser, si12)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        return {"immediate"}

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

rs2 = operand_def(IntRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI12]) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, immediate: int | IntegerAttr[SI12] | str | LabelAttr, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    immediate: int | IntegerAttr[SI12] | str | LabelAttr,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si12)
    elif isinstance(immediate, str):
        immediate = LabelAttr(immediate)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1073
1074
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rs1, self.rs2, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1076
1077
1078
1079
1080
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["immediate"] = parse_immediate_value(parser, si12)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1082
1083
1084
1085
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    return {"immediate"}

RsRsIntegerOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have two source registers.

Source code in xdsl/dialects/riscv/abstract_ops.py 
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
class RsRsIntegerOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have two source
    registers.
    """

    rs1 = operand_def(IntRegisterType)
    rs2 = operand_def(IntRegisterType)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        rs2: Operation | SSAValue,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1, rs2],
            attributes={
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rs1, self.rs2

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

rs2 = operand_def(IntRegisterType) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, rs2: Operation | SSAValue, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
def __init__(
    self,
    rs1: Operation | SSAValue,
    rs2: Operation | SSAValue,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1, rs2],
        attributes={
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1112
1113
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rs1, self.rs2

NullaryOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations that have neither sources nor destinations.

Source code in xdsl/dialects/riscv/abstract_ops.py 
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
class NullaryOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations that have neither sources nor destinations.
    """

    def __init__(
        self,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            attributes={
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return ()

    @classmethod
    def parse_unresolved_operands(cls, parser: Parser) -> list[UnresolvedOperand]:
        return []

    def print_op_type(self, printer: Printer) -> None:
        return

    @classmethod
    def parse_op_type(
        cls, parser: Parser
    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
        return (), ()

__init__(*, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
def __init__(
    self,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        attributes={
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1135
1136
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return ()

parse_unresolved_operands(parser: Parser) -> list[UnresolvedOperand] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1138
1139
1140
@classmethod
def parse_unresolved_operands(cls, parser: Parser) -> list[UnresolvedOperand]:
    return []

print_op_type(printer: Printer) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
1142
1143
def print_op_type(self, printer: Printer) -> None:
    return

parse_op_type(parser: Parser) -> tuple[Sequence[Attribute], Sequence[Attribute]] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1145
1146
1147
1148
1149
@classmethod
def parse_op_type(
    cls, parser: Parser
) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
    return (), ()

CsrReadWriteOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations performing a swap to/from a CSR.

The 'writeonly' attribute controls the actual behaviour of the operation: * when True, the operation writes the rs value to the CSR but never reads it and in this case rd must be allocated to x0 * when False, a proper atomic swap is performed and the previous CSR value is returned in rd

Source code in xdsl/dialects/riscv/abstract_ops.py 
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
class CsrReadWriteOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations performing a swap to/from a CSR.

    The 'writeonly' attribute controls the actual behaviour of the operation:
    * when True, the operation writes the rs value to the CSR but never reads it and
      in this case rd *must* be allocated to x0
    * when False, a proper atomic swap is performed and the previous CSR value is
      returned in rd
    """

    rd = result_def(IntRegisterType)
    rs1 = operand_def(IntRegisterType)
    csr = attr_def(IntegerAttr)
    writeonly = opt_attr_def(UnitAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        csr: IntegerAttr,
        *,
        writeonly: bool = False,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1],
            attributes={
                "csr": csr,
                "writeonly": UnitAttr() if writeonly else None,
                "comment": comment,
            },
            result_types=[rd],
        )

    def verify_(self) -> None:
        if not self.writeonly:
            return
        if is_non_zero(self.rd.type):
            raise VerifyException(
                "When in 'writeonly' mode, destination must be register x0 (a.k.a. 'zero'), "
                f"not '{self.rd.type.register_name.data}'"
            )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.csr, self.rs1

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["csr"] = IntegerAttr(
            parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
            IntegerType(32),
        )
        if parser.parse_optional_punctuation(",") is not None:
            if (flag := parser.parse_str_literal("Expected 'w' flag")) != "w":
                parser.raise_error(f"Expected 'w' flag, got '{flag}'")
            attributes["writeonly"] = UnitAttr()
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        self.csr.print_without_type(printer)
        if self.writeonly is not None:
            printer.print_string(', "w"')
        return {"csr", "writeonly"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

csr = attr_def(IntegerAttr) class-attribute instance-attribute

writeonly = opt_attr_def(UnitAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, csr: IntegerAttr, *, writeonly: bool = False, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
def __init__(
    self,
    rs1: Operation | SSAValue,
    csr: IntegerAttr,
    *,
    writeonly: bool = False,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1],
        attributes={
            "csr": csr,
            "writeonly": UnitAttr() if writeonly else None,
            "comment": comment,
        },
        result_types=[rd],
    )

verify_() -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
1189
1190
1191
1192
1193
1194
1195
1196
def verify_(self) -> None:
    if not self.writeonly:
        return
    if is_non_zero(self.rd.type):
        raise VerifyException(
            "When in 'writeonly' mode, destination must be register x0 (a.k.a. 'zero'), "
            f"not '{self.rd.type.register_name.data}'"
        )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1198
1199
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.csr, self.rs1

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["csr"] = IntegerAttr(
        parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
        IntegerType(32),
    )
    if parser.parse_optional_punctuation(",") is not None:
        if (flag := parser.parse_str_literal("Expected 'w' flag")) != "w":
            parser.raise_error(f"Expected 'w' flag, got '{flag}'")
        attributes["writeonly"] = UnitAttr()
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1214
1215
1216
1217
1218
1219
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    self.csr.print_without_type(printer)
    if self.writeonly is not None:
        printer.print_string(', "w"')
    return {"csr", "writeonly"}

CsrBitwiseOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations performing a masked bitwise operation on the CSR while returning the original value.

The 'readonly' attribute controls the actual behaviour of the operation: * when True, the operation is guaranteed to have no side effects that can be potentially related to writing to a CSR; in this case rs must be allocated to x0 * when False, the bitwise operations is performed and any side effect related to writing to a CSR takes place even if the mask in rs has no actual bits set.

Source code in xdsl/dialects/riscv/abstract_ops.py 
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
class CsrBitwiseOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations performing a masked bitwise operation on the
    CSR while returning the original value.

    The 'readonly' attribute controls the actual behaviour of the operation:
    * when True, the operation is guaranteed to have no side effects that can
      be potentially related to writing to a CSR; in this case rs *must be
      allocated to x0*
    * when False, the bitwise operations is performed and any side effect related
      to writing to a CSR takes place even if the mask in rs has no actual bits set.
    """

    rd = result_def(IntRegisterType)
    rs1 = operand_def(IntRegisterType)
    csr = attr_def(IntegerAttr)
    readonly = opt_attr_def(UnitAttr)

    def __init__(
        self,
        rs1: Operation | SSAValue,
        csr: IntegerAttr,
        *,
        readonly: bool = False,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[rs1],
            attributes={
                "csr": csr,
                "readonly": UnitAttr() if readonly else None,
                "comment": comment,
            },
            result_types=[rd],
        )

    def verify_(self) -> None:
        if not self.readonly:
            return
        assert isinstance(self.rs1.type, IntRegisterType)
        if is_non_zero(self.rs1.type):
            raise VerifyException(
                "When in 'readonly' mode, source must be register x0 (a.k.a. 'zero'), "
                f"not '{self.rs1.type.register_name.data}'"
            )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.csr, self.rs1

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["csr"] = IntegerAttr(
            parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
            IntegerType(32),
        )
        if parser.parse_optional_punctuation(",") is not None:
            if (flag := parser.parse_str_literal("Expected 'r' flag")) != "r":
                parser.raise_error(f"Expected 'r' flag, got '{flag}'")
            attributes["readonly"] = UnitAttr()
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(", ")
        self.csr.print_without_type(printer)
        if self.readonly is not None:
            printer.print_string(', "r"')
        return {"csr", "readonly"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

rs1 = operand_def(IntRegisterType) class-attribute instance-attribute

csr = attr_def(IntegerAttr) class-attribute instance-attribute

readonly = opt_attr_def(UnitAttr) class-attribute instance-attribute

__init__(rs1: Operation | SSAValue, csr: IntegerAttr, *, readonly: bool = False, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
def __init__(
    self,
    rs1: Operation | SSAValue,
    csr: IntegerAttr,
    *,
    readonly: bool = False,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[rs1],
        attributes={
            "csr": csr,
            "readonly": UnitAttr() if readonly else None,
            "comment": comment,
        },
        result_types=[rd],
    )

verify_() -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
1261
1262
1263
1264
1265
1266
1267
1268
1269
def verify_(self) -> None:
    if not self.readonly:
        return
    assert isinstance(self.rs1.type, IntRegisterType)
    if is_non_zero(self.rs1.type):
        raise VerifyException(
            "When in 'readonly' mode, source must be register x0 (a.k.a. 'zero'), "
            f"not '{self.rs1.type.register_name.data}'"
        )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1271
1272
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.csr, self.rs1

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["csr"] = IntegerAttr(
        parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
        IntegerType(32),
    )
    if parser.parse_optional_punctuation(",") is not None:
        if (flag := parser.parse_str_literal("Expected 'r' flag")) != "r":
            parser.raise_error(f"Expected 'r' flag, got '{flag}'")
        attributes["readonly"] = UnitAttr()
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1287
1288
1289
1290
1291
1292
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(", ")
    self.csr.print_without_type(printer)
    if self.readonly is not None:
        printer.print_string(', "r"')
    return {"csr", "readonly"}

CsrReadWriteImmOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations performing a write immediate to/read from a CSR.

The 'writeonly' attribute controls the actual behaviour of the operation: * when True, the operation writes the rs value to the CSR but never reads it and in this case rd must be allocated to x0 * when False, a proper atomic swap is performed and the previous CSR value is returned in rd

Source code in xdsl/dialects/riscv/abstract_ops.py 
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
class CsrReadWriteImmOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations performing a write immediate to/read from a CSR.

    The 'writeonly' attribute controls the actual behaviour of the operation:
    * when True, the operation writes the rs value to the CSR but never reads it and
      in this case rd *must* be allocated to x0
    * when False, a proper atomic swap is performed and the previous CSR value is
      returned in rd
    """

    rd = result_def(IntRegisterType)
    csr = attr_def(IntegerAttr)
    immediate = attr_def(IntegerAttr)
    writeonly = opt_attr_def(UnitAttr)

    def __init__(
        self,
        csr: IntegerAttr,
        immediate: IntegerAttr,
        *,
        writeonly: bool = False,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            attributes={
                "csr": csr,
                "immediate": immediate,
                "writeonly": UnitAttr() if writeonly else None,
                "comment": comment,
            },
            result_types=[rd],
        )

    def verify_(self) -> None:
        if self.writeonly is None:
            return
        if is_non_zero(self.rd.type):
            raise VerifyException(
                "When in 'writeonly' mode, destination must be register x0 (a.k.a. 'zero'), "
                f"not '{self.rd.type.register_name.data}'"
            )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return self.rd, self.csr, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["csr"] = IntegerAttr(
            parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
            IntegerType(32),
        )
        parser.parse_punctuation(",")
        attributes["immediate"] = parse_immediate_value(parser, IntegerType(32))
        if parser.parse_optional_punctuation(",") is not None:
            if (flag := parser.parse_str_literal("Expected 'w' flag")) != "w":
                parser.raise_error(f"Expected 'w' flag, got '{flag}'")
            attributes["writeonly"] = UnitAttr()
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(" ")
        self.csr.print_without_type(printer)
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        if self.writeonly is not None:
            printer.print_string(', "w"')
        return {"csr", "immediate", "writeonly"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

csr = attr_def(IntegerAttr) class-attribute instance-attribute

immediate = attr_def(IntegerAttr) class-attribute instance-attribute

writeonly = opt_attr_def(UnitAttr) class-attribute instance-attribute

__init__(csr: IntegerAttr, immediate: IntegerAttr, *, writeonly: bool = False, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
def __init__(
    self,
    csr: IntegerAttr,
    immediate: IntegerAttr,
    *,
    writeonly: bool = False,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        attributes={
            "csr": csr,
            "immediate": immediate,
            "writeonly": UnitAttr() if writeonly else None,
            "comment": comment,
        },
        result_types=[rd],
    )

verify_() -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
1332
1333
1334
1335
1336
1337
1338
1339
def verify_(self) -> None:
    if self.writeonly is None:
        return
    if is_non_zero(self.rd.type):
        raise VerifyException(
            "When in 'writeonly' mode, destination must be register x0 (a.k.a. 'zero'), "
            f"not '{self.rd.type.register_name.data}'"
        )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1341
1342
def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return self.rd, self.csr, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["csr"] = IntegerAttr(
        parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
        IntegerType(32),
    )
    parser.parse_punctuation(",")
    attributes["immediate"] = parse_immediate_value(parser, IntegerType(32))
    if parser.parse_optional_punctuation(",") is not None:
        if (flag := parser.parse_str_literal("Expected 'w' flag")) != "w":
            parser.raise_error(f"Expected 'w' flag, got '{flag}'")
        attributes["writeonly"] = UnitAttr()
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1359
1360
1361
1362
1363
1364
1365
1366
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(" ")
    self.csr.print_without_type(printer)
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    if self.writeonly is not None:
        printer.print_string(', "w"')
    return {"csr", "immediate", "writeonly"}

CsrBitwiseImmOperation

Bases: RISCVCustomFormatOperation, RISCVInstruction, ABC

A base class for RISC-V operations performing a masked bitwise operation on the CSR while returning the original value. The bitmask is specified in the 'immediate' attribute.

The 'immediate' attribute controls the actual behaviour of the operation: * when equals to zero, the operation is guaranteed to have no side effects that can be potentially related to writing to a CSR; * when not equal to zero, any side effect related to writing to a CSR takes place.

Source code in xdsl/dialects/riscv/abstract_ops.py 
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
class CsrBitwiseImmOperation(RISCVCustomFormatOperation, RISCVInstruction, ABC):
    """
    A base class for RISC-V operations performing a masked bitwise operation on the
    CSR while returning the original value. The bitmask is specified in the 'immediate'
    attribute.

    The 'immediate' attribute controls the actual behaviour of the operation:
    * when equals to zero, the operation is guaranteed to have no side effects
      that can be potentially related to writing to a CSR;
    * when not equal to zero, any side effect related to writing to a CSR takes
      place.
    """

    rd = result_def(IntRegisterType)
    csr = attr_def(IntegerAttr)
    immediate = attr_def(IntegerAttr)

    def __init__(
        self,
        csr: IntegerAttr,
        immediate: IntegerAttr,
        *,
        rd: IntRegisterType = Registers.UNALLOCATED_INT,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            attributes={
                "csr": csr,
                "immediate": immediate,
                "comment": comment,
            },
            result_types=[rd],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return self.rd, self.csr, self.immediate

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["csr"] = IntegerAttr(
            parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
            IntegerType(32),
        )
        parser.parse_punctuation(",")
        attributes["immediate"] = parse_immediate_value(parser, IntegerType(32))
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(" ")
        self.csr.print_without_type(printer)
        printer.print_string(", ")
        print_immediate_value(printer, self.immediate)
        return {"csr", "immediate"}

rd = result_def(IntRegisterType) class-attribute instance-attribute

csr = attr_def(IntegerAttr) class-attribute instance-attribute

immediate = attr_def(IntegerAttr) class-attribute instance-attribute

__init__(csr: IntegerAttr, immediate: IntegerAttr, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
def __init__(
    self,
    csr: IntegerAttr,
    immediate: IntegerAttr,
    *,
    rd: IntRegisterType = Registers.UNALLOCATED_INT,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        attributes={
            "csr": csr,
            "immediate": immediate,
            "comment": comment,
        },
        result_types=[rd],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1405
1406
def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return self.rd, self.csr, self.immediate

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["csr"] = IntegerAttr(
        parser.parse_integer(allow_boolean=False, context_msg="Expected csr"),
        IntegerType(32),
    )
    parser.parse_punctuation(",")
    attributes["immediate"] = parse_immediate_value(parser, IntegerType(32))
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/riscv/abstract_ops.py 
1419
1420
1421
1422
1423
1424
def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(" ")
    self.csr.print_without_type(printer)
    printer.print_string(", ")
    print_immediate_value(printer, self.immediate)
    return {"csr", "immediate"}

GetAnyRegisterOperation

Bases: RISCVCustomFormatOperation, RISCVAsmOperation, RISCVRegallocOperation, ABC, Generic[RDInvT]

This instruction allows us to create an SSAValue with for a given register name. This is useful for bridging the RISC-V convention that stores the result of function calls in a0 and a1 into SSA form.

For example, to generate this assembly:

jal my_func
add a0 s0 a0

One needs to do the following:

rhs = rv32.GetRegisterOp(Registers.s0).res
riscv.JalOp("my_func")
lhs = rv32.GetRegisterOp(Registers.A0).res
sum = riscv.AddOp(lhs, rhs, Registers.A0).rd
Source code in xdsl/dialects/riscv/abstract_ops.py 
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
class GetAnyRegisterOperation(
    RISCVCustomFormatOperation,
    RISCVAsmOperation,
    RISCVRegallocOperation,
    ABC,
    Generic[RDInvT],
):
    """
    This instruction allows us to create an SSAValue with for a given register name. This
    is useful for bridging the RISC-V convention that stores the result of function calls
    in `a0` and `a1` into SSA form.

    For example, to generate this assembly:
    ```
    jal my_func
    add a0 s0 a0
    ```

    One needs to do the following:

    ``` python
    rhs = rv32.GetRegisterOp(Registers.s0).res
    riscv.JalOp("my_func")
    lhs = rv32.GetRegisterOp(Registers.A0).res
    sum = riscv.AddOp(lhs, rhs, Registers.A0).rd
    ```
    """

    res = result_def(RDInvT)

    traits = traits_def(Pure())

    def __init__(
        self,
        register_type: RDInvT,
    ):
        super().__init__(result_types=[register_type])

    def assembly_line(self) -> str | None:
        # Don't print assembly for creating a SSA value representing register
        return None

    @classmethod
    def parse_op_type(
        cls, parser: Parser
    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
        parser.parse_punctuation(":")
        res_type = parser.parse_attribute()
        return (), (res_type,)

    def print_op_type(self, printer: Printer) -> None:
        printer.print_string(" : ")
        printer.print_attribute(self.res.type)

res = result_def(RDInvT) class-attribute instance-attribute

traits = traits_def(Pure()) class-attribute instance-attribute

__init__(register_type: RDInvT)

Source code in xdsl/dialects/riscv/abstract_ops.py 
1459
1460
1461
1462
1463
def __init__(
    self,
    register_type: RDInvT,
):
    super().__init__(result_types=[register_type])

assembly_line() -> str | None

Source code in xdsl/dialects/riscv/abstract_ops.py 
1465
1466
1467
def assembly_line(self) -> str | None:
    # Don't print assembly for creating a SSA value representing register
    return None

parse_op_type(parser: Parser) -> tuple[Sequence[Attribute], Sequence[Attribute]] classmethod

Source code in xdsl/dialects/riscv/abstract_ops.py 
1469
1470
1471
1472
1473
1474
1475
@classmethod
def parse_op_type(
    cls, parser: Parser
) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
    parser.parse_punctuation(":")
    res_type = parser.parse_attribute()
    return (), (res_type,)

print_op_type(printer: Printer) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
1477
1478
1479
def print_op_type(self, printer: Printer) -> None:
    printer.print_string(" : ")
    printer.print_attribute(self.res.type)

assembly_arg_str(arg: AssemblyInstructionArg) -> str

Source code in xdsl/dialects/riscv/abstract_ops.py 
224
225
226
227
228
229
230
231
232
233
234
235
236
def assembly_arg_str(arg: AssemblyInstructionArg) -> str:
    if isinstance(arg, SSAValue):
        if not isinstance(t := arg.type, RegisterType):
            raise ValueError(f"Unexpected register type {t}")
        return t.register_name.data
    elif isinstance(arg, IntegerAttr):
        return f"{arg.value.data}"
    elif isinstance(arg, LabelAttr):
        return arg.data
    elif isinstance(arg, RegisterType):
        return arg.register_name.data

    return arg

print_assembly(module: ModuleOp, output: IO[str]) -> None

Source code in xdsl/dialects/riscv/abstract_ops.py 
239
240
241
def print_assembly(module: ModuleOp, output: IO[str]) -> None:
    printer = AssemblyPrinter(stream=output)
    printer.print_module(module)

riscv_code(module: ModuleOp) -> str

Source code in xdsl/dialects/riscv/abstract_ops.py 
244
245
246
247
def riscv_code(module: ModuleOp) -> str:
    stream = StringIO()
    print_assembly(module, stream)
    return stream.getvalue()