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Seq

seq

CIRCT’s seq dialect.

See external documentation.

clock = ClockType() module-attribute

Seq = Dialect('seq', [ClockDividerOp, CompRegOp, ConstClockOp], [ClockType, ClockConstAttr]) module-attribute

ClockType dataclass

Bases: ParametrizedAttribute, TypeAttribute

A type for clock-carrying wires. Signals which can be used to drive the clock input of sequential operations.

Source code in xdsl/dialects/seq.py 
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@irdl_attr_definition
class ClockType(ParametrizedAttribute, TypeAttribute):
    """
    A type for clock-carrying wires. Signals which can be used to drive the clock input of sequential operations.
    """

    name = "seq.clock"

name = 'seq.clock' class-attribute instance-attribute

ClockDividerOp

Bases: IRDLOperation

Produces a clock divided by a power of two

Source code in xdsl/dialects/seq.py 
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@irdl_op_definition
class ClockDividerOp(IRDLOperation):
    """Produces a clock divided by a power of two"""

    name = "seq.clock_div"

    pow2 = attr_def(IntegerAttr)
    clockIn = operand_def(ClockType)
    clockOut = result_def(ClockType)

    def __init__(self, clockIn: SSAValue | Operation, pow2: int | IntegerAttr):
        if isinstance(pow2, int):
            pow2 = IntegerAttr(pow2, IntegerType(8))
        super().__init__(
            operands=[clockIn], attributes={"pow2": pow2}, result_types=[clock]
        )

    def verify_(self) -> None:
        if self.pow2.type != IntegerType(8):
            raise VerifyException("pow2 has to be an 8-bit signless integer")
        if self.pow2.value.data.bit_count() != 1:
            raise VerifyException(
                f"divider value {self.pow2.value.data} is not a power of 2"
            )

    @classmethod
    def parse(cls, parser: Parser):
        input_ = parser.parse_operand()
        parser.parse_keyword("by")
        divider = parser.parse_integer()
        return cls(input_, divider)

    def print(self, printer: Printer):
        printer.print_string(" ")
        printer.print_operand(self.clockIn)
        printer.print_string(" by ")
        self.pow2.print_without_type(printer)

name = 'seq.clock_div' class-attribute instance-attribute

pow2 = attr_def(IntegerAttr) class-attribute instance-attribute

clockIn = operand_def(ClockType) class-attribute instance-attribute

clockOut = result_def(ClockType) class-attribute instance-attribute

__init__(clockIn: SSAValue | Operation, pow2: int | IntegerAttr)

Source code in xdsl/dialects/seq.py 
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def __init__(self, clockIn: SSAValue | Operation, pow2: int | IntegerAttr):
    if isinstance(pow2, int):
        pow2 = IntegerAttr(pow2, IntegerType(8))
    super().__init__(
        operands=[clockIn], attributes={"pow2": pow2}, result_types=[clock]
    )

verify_() -> None

Source code in xdsl/dialects/seq.py 
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def verify_(self) -> None:
    if self.pow2.type != IntegerType(8):
        raise VerifyException("pow2 has to be an 8-bit signless integer")
    if self.pow2.value.data.bit_count() != 1:
        raise VerifyException(
            f"divider value {self.pow2.value.data} is not a power of 2"
        )

parse(parser: Parser) classmethod

Source code in xdsl/dialects/seq.py 
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@classmethod
def parse(cls, parser: Parser):
    input_ = parser.parse_operand()
    parser.parse_keyword("by")
    divider = parser.parse_integer()
    return cls(input_, divider)

print(printer: Printer)

Source code in xdsl/dialects/seq.py 
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def print(self, printer: Printer):
    printer.print_string(" ")
    printer.print_operand(self.clockIn)
    printer.print_string(" by ")
    self.pow2.print_without_type(printer)

CompRegOp

Bases: IRDLOperation

Register a value, storing it for one cycle.

Source code in xdsl/dialects/seq.py 
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@irdl_op_definition
class CompRegOp(IRDLOperation):
    """
    Register a value, storing it for one cycle.
    """

    name = "seq.compreg"

    DATA_TYPE: ClassVar = VarConstraint("DataType", AnyAttr())

    inner_sym = opt_attr_def(InnerSymAttr)
    input = operand_def(DATA_TYPE)
    clk = operand_def(clock)
    reset = opt_operand_def(i1)
    reset_value = opt_operand_def(DATA_TYPE)
    power_on_value = opt_operand_def(DATA_TYPE)
    data = result_def(DATA_TYPE)

    irdl_options = (AttrSizedOperandSegments(),)

    assembly_format = (
        "(`sym` $inner_sym^)? $input `,` $clk "
        "(`reset` $reset^ `,` $reset_value)? "
        "(`powerOn` $power_on_value^)? "
        "attr-dict `:` type($input)"
    )

    def __init__(
        self,
        input: SSAValue,
        clk: SSAValue,
        reset: tuple[SSAValue, SSAValue] | None = None,
        power_on_value: SSAValue | None = None,
    ):
        super().__init__(
            operands=[
                input,
                clk,
                reset[0] if reset is not None else None,
                reset[1] if reset is not None else None,
                power_on_value,
            ],
            result_types=[input.type],
        )

    def verify_(self):
        if (self.reset is None) != (self.reset_value is None):
            raise VerifyException("Both reset and reset_value must be set when one is")

name = 'seq.compreg' class-attribute instance-attribute

DATA_TYPE: ClassVar = VarConstraint('DataType', AnyAttr()) class-attribute instance-attribute

inner_sym = opt_attr_def(InnerSymAttr) class-attribute instance-attribute

input = operand_def(DATA_TYPE) class-attribute instance-attribute

clk = operand_def(clock) class-attribute instance-attribute

reset = opt_operand_def(i1) class-attribute instance-attribute

reset_value = opt_operand_def(DATA_TYPE) class-attribute instance-attribute

power_on_value = opt_operand_def(DATA_TYPE) class-attribute instance-attribute

data = result_def(DATA_TYPE) class-attribute instance-attribute

irdl_options = (AttrSizedOperandSegments(),) class-attribute instance-attribute

assembly_format = '(`sym` $inner_sym^)? $input `,` $clk (`reset` $reset^ `,` $reset_value)? (`powerOn` $power_on_value^)? attr-dict `:` type($input)' class-attribute instance-attribute

__init__(input: SSAValue, clk: SSAValue, reset: tuple[SSAValue, SSAValue] | None = None, power_on_value: SSAValue | None = None)

Source code in xdsl/dialects/seq.py 
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def __init__(
    self,
    input: SSAValue,
    clk: SSAValue,
    reset: tuple[SSAValue, SSAValue] | None = None,
    power_on_value: SSAValue | None = None,
):
    super().__init__(
        operands=[
            input,
            clk,
            reset[0] if reset is not None else None,
            reset[1] if reset is not None else None,
            power_on_value,
        ],
        result_types=[input.type],
    )

verify_()

Source code in xdsl/dialects/seq.py 
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def verify_(self):
    if (self.reset is None) != (self.reset_value is None):
        raise VerifyException("Both reset and reset_value must be set when one is")

ClockConstAttrData

Bases: Enum

Source code in xdsl/dialects/seq.py 
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class ClockConstAttrData(Enum):
    LOW = 0
    HIGH = 1

LOW = 0 class-attribute instance-attribute

HIGH = 1 class-attribute instance-attribute

ClockConstAttr dataclass

Bases: Data[ClockConstAttrData]

Clock constant.

This attribute diverges slightly from the upstream implementation as xDSL does not allow completely unstructured parsing and printing of attributes (for good reasons).

Source code in xdsl/dialects/seq.py 
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@irdl_attr_definition
class ClockConstAttr(Data[ClockConstAttrData]):
    """
    Clock constant.

    This attribute diverges slightly from the upstream implementation
    as xDSL does not allow completely unstructured parsing and printing
    of attributes (for good reasons).
    """

    name = "seq.clock_constant"

    @classmethod
    def parse_parameter(cls, parser: AttrParser) -> ClockConstAttrData:
        with parser.in_angle_brackets():
            return ClockConstAttr.parse_parameter_free_standing(parser)

    @classmethod
    def parse_parameter_free_standing(cls, parser: AttrParser) -> ClockConstAttrData:
        if parser.parse_optional_keyword("low") is not None:
            return ClockConstAttrData.LOW
        if parser.parse_optional_keyword("high") is not None:
            return ClockConstAttrData.HIGH
        parser.raise_error("Expected either low or high clock value")

    def print_parameter(self, printer: Printer) -> None:
        with printer.in_angle_brackets():
            self.print_parameter_free_standing(printer)

    def print_parameter_free_standing(self, printer: Printer) -> None:
        match self.data:
            case ClockConstAttrData.LOW:
                printer.print_string("low")
            case ClockConstAttrData.HIGH:
                printer.print_string("high")

name = 'seq.clock_constant' class-attribute instance-attribute

parse_parameter(parser: AttrParser) -> ClockConstAttrData classmethod

Source code in xdsl/dialects/seq.py 
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@classmethod
def parse_parameter(cls, parser: AttrParser) -> ClockConstAttrData:
    with parser.in_angle_brackets():
        return ClockConstAttr.parse_parameter_free_standing(parser)

parse_parameter_free_standing(parser: AttrParser) -> ClockConstAttrData classmethod

Source code in xdsl/dialects/seq.py 
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@classmethod
def parse_parameter_free_standing(cls, parser: AttrParser) -> ClockConstAttrData:
    if parser.parse_optional_keyword("low") is not None:
        return ClockConstAttrData.LOW
    if parser.parse_optional_keyword("high") is not None:
        return ClockConstAttrData.HIGH
    parser.raise_error("Expected either low or high clock value")

print_parameter(printer: Printer) -> None

Source code in xdsl/dialects/seq.py 
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def print_parameter(self, printer: Printer) -> None:
    with printer.in_angle_brackets():
        self.print_parameter_free_standing(printer)

print_parameter_free_standing(printer: Printer) -> None

Source code in xdsl/dialects/seq.py 
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def print_parameter_free_standing(self, printer: Printer) -> None:
    match self.data:
        case ClockConstAttrData.LOW:
            printer.print_string("low")
        case ClockConstAttrData.HIGH:
            printer.print_string("high")

ConstClockOp dataclass

Bases: IRDLOperation

The constant operation produces a constant clock value.

Source code in xdsl/dialects/seq.py 
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@irdl_op_definition
class ConstClockOp(IRDLOperation):
    """
    The constant operation produces a constant clock value.
    """

    name = "seq.const_clock"

    value = attr_def(ClockConstAttr)
    result = result_def(clock)

    @classmethod
    def parse(cls, parser: Parser) -> "ConstClockOp":
        value = ClockConstAttr(ClockConstAttr.parse_parameter_free_standing(parser))
        attrs = parser.parse_optional_attr_dict_with_reserved_attr_names(("value",))
        attrs_data = dict(attrs.data) if attrs is not None else {}
        attrs_data["value"] = value
        return ConstClockOp.create(attributes=attrs_data, result_types=[clock])

    def print(self, printer: Printer):
        printer.print_string(" ")
        self.value.print_parameter_free_standing(printer)
        printer.print_op_attributes(self.attributes, reserved_attr_names=("value",))

name = 'seq.const_clock' class-attribute instance-attribute

value = attr_def(ClockConstAttr) class-attribute instance-attribute

result = result_def(clock) class-attribute instance-attribute

parse(parser: Parser) -> ConstClockOp classmethod

Source code in xdsl/dialects/seq.py 
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@classmethod
def parse(cls, parser: Parser) -> "ConstClockOp":
    value = ClockConstAttr(ClockConstAttr.parse_parameter_free_standing(parser))
    attrs = parser.parse_optional_attr_dict_with_reserved_attr_names(("value",))
    attrs_data = dict(attrs.data) if attrs is not None else {}
    attrs_data["value"] = value
    return ConstClockOp.create(attributes=attrs_data, result_types=[clock])

print(printer: Printer)

Source code in xdsl/dialects/seq.py 
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def print(self, printer: Printer):
    printer.print_string(" ")
    self.value.print_parameter_free_standing(printer)
    printer.print_op_attributes(self.attributes, reserved_attr_names=("value",))