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Replace incompatible fpga

replace_incompatible_fpga

ReplaceCopySignOpByXilinxMath dataclass

Bases: RewritePattern

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@dataclass
class ReplaceCopySignOpByXilinxMath(RewritePattern):
    def __init__(self, op: builtin.ModuleOp):
        self.module = op
        self.func_def_declaration = False

    @op_type_rewrite_pattern
    def match_and_rewrite(self, op: CopySignOp, rewriter: PatternRewriter, /):
        if not self.func_def_declaration:
            func_def = FuncOp.external("llvm.copysign.f64", [f64, f64], [f64])
            self.module.body.block.add_op(func_def)
            self.func_def_declaration = True

        call = CallOp("llvm.copysign.f64", [op.lhs, op.rhs], [f64])

        rewriter.replace(op, [call])

module = op instance-attribute

func_def_declaration = False instance-attribute

__init__(op: builtin.ModuleOp)

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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def __init__(self, op: builtin.ModuleOp):
    self.module = op
    self.func_def_declaration = False

match_and_rewrite(op: CopySignOp, rewriter: PatternRewriter)

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@op_type_rewrite_pattern
def match_and_rewrite(self, op: CopySignOp, rewriter: PatternRewriter, /):
    if not self.func_def_declaration:
        func_def = FuncOp.external("llvm.copysign.f64", [f64, f64], [f64])
        self.module.body.block.add_op(func_def)
        self.func_def_declaration = True

    call = CallOp("llvm.copysign.f64", [op.lhs, op.rhs], [f64])

    rewriter.replace(op, [call])

ReplaceMaximumfByXilinxMath dataclass

Bases: RewritePattern

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@dataclass
class ReplaceMaximumfByXilinxMath(RewritePattern):
    def __init__(self, op: builtin.ModuleOp):
        self.module = op
        self.func_def_declaration = False

    @op_type_rewrite_pattern
    def match_and_rewrite(self, op: MaximumfOp, rewriter: PatternRewriter, /):
        if not self.func_def_declaration:
            func_def = FuncOp.external("llvm.maxnum.f64", [f64, f64], [f64])
            self.module.body.block.add_op(func_def)
            self.func_def_declaration = True

        call = CallOp("llvm.maxnum.f64", [op.lhs, op.rhs], [f64])

        rewriter.replace(op, [call])

module = op instance-attribute

func_def_declaration = False instance-attribute

__init__(op: builtin.ModuleOp)

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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def __init__(self, op: builtin.ModuleOp):
    self.module = op
    self.func_def_declaration = False

match_and_rewrite(op: MaximumfOp, rewriter: PatternRewriter)

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@op_type_rewrite_pattern
def match_and_rewrite(self, op: MaximumfOp, rewriter: PatternRewriter, /):
    if not self.func_def_declaration:
        func_def = FuncOp.external("llvm.maxnum.f64", [f64, f64], [f64])
        self.module.body.block.add_op(func_def)
        self.func_def_declaration = True

    call = CallOp("llvm.maxnum.f64", [op.lhs, op.rhs], [f64])

    rewriter.replace(op, [call])

ReplaceAbsOpByXilinxMath dataclass

Bases: RewritePattern

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@dataclass
class ReplaceAbsOpByXilinxMath(RewritePattern):
    def __init__(self, op: builtin.ModuleOp):
        self.module = op
        self.func_def_declaration = False

    @op_type_rewrite_pattern
    def match_and_rewrite(self, op: AbsFOp, rewriter: PatternRewriter, /):
        if not self.func_def_declaration:
            func_def = FuncOp.external("llvm.fabs.f64", [f64], [f64])
            self.module.body.block.add_op(func_def)
            self.func_def_declaration = True

        call = CallOp("llvm.fabs.f64", [op.operand], [f64])

        rewriter.replace(op, [call])

module = op instance-attribute

func_def_declaration = False instance-attribute

__init__(op: builtin.ModuleOp)

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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def __init__(self, op: builtin.ModuleOp):
    self.module = op
    self.func_def_declaration = False

match_and_rewrite(op: AbsFOp, rewriter: PatternRewriter)

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@op_type_rewrite_pattern
def match_and_rewrite(self, op: AbsFOp, rewriter: PatternRewriter, /):
    if not self.func_def_declaration:
        func_def = FuncOp.external("llvm.fabs.f64", [f64], [f64])
        self.module.body.block.add_op(func_def)
        self.func_def_declaration = True

    call = CallOp("llvm.fabs.f64", [op.operand], [f64])

    rewriter.replace(op, [call])

ReplaceIncompatibleFPGA dataclass

Bases: ModulePass

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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@dataclass(frozen=True)
class ReplaceIncompatibleFPGA(ModulePass):
    name = "replace-incompatible-fpga"

    def apply(self, ctx: Context, op: builtin.ModuleOp) -> None:
        def gen_greedy_walkers(
            passes: list[RewritePattern],
        ) -> list[PatternRewriteWalker]:
            # Creates a greedy walker for each pass, so that they can be run sequentially even after
            # matching
            walkers: list[PatternRewriteWalker] = []

            for i in range(len(passes)):
                walkers.append(
                    PatternRewriteWalker(
                        GreedyRewritePatternApplier([passes[i]]), apply_recursively=True
                    )
                )

            return walkers

        walkers = gen_greedy_walkers(
            [
                # ReplaceCopySignOpByEquivalent(),
                ReplaceCopySignOpByXilinxMath(op),
                # ReplaceMaximumfOpByEquivalent(),
                ReplaceMaximumfByXilinxMath(op),
                # ReplaceAbsOpByEquivalent(),
                ReplaceAbsOpByXilinxMath(op),
            ]
        )

        for walker in walkers:
            walker.rewrite_module(op)

name = 'replace-incompatible-fpga' class-attribute instance-attribute

__init__() -> None

apply(ctx: Context, op: builtin.ModuleOp) -> None

Source code in xdsl/transforms/experimental/replace_incompatible_fpga.py 
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def apply(self, ctx: Context, op: builtin.ModuleOp) -> None:
    def gen_greedy_walkers(
        passes: list[RewritePattern],
    ) -> list[PatternRewriteWalker]:
        # Creates a greedy walker for each pass, so that they can be run sequentially even after
        # matching
        walkers: list[PatternRewriteWalker] = []

        for i in range(len(passes)):
            walkers.append(
                PatternRewriteWalker(
                    GreedyRewritePatternApplier([passes[i]]), apply_recursively=True
                )
            )

        return walkers

    walkers = gen_greedy_walkers(
        [
            # ReplaceCopySignOpByEquivalent(),
            ReplaceCopySignOpByXilinxMath(op),
            # ReplaceMaximumfOpByEquivalent(),
            ReplaceMaximumfByXilinxMath(op),
            # ReplaceAbsOpByEquivalent(),
            ReplaceAbsOpByXilinxMath(op),
        ]
    )

    for walker in walkers:
        walker.rewrite_module(op)