Riscv allocate registers

riscv_allocate_registers

RISCVAllocateRegistersPass dataclass

Bases: ModulePass

Allocates unallocated registers in the module.

Source code in xdsl/transforms/riscv_allocate_registers.py

@dataclass(frozen=True)
class RISCVAllocateRegistersPass(ModulePass):
    """
    Allocates unallocated registers in the module.
    """

    name = "riscv-allocate-registers"

    allocation_strategy: str = "LivenessBlockNaive"

    add_regalloc_stats: bool = False
    """
    Inserts a comment with register allocation info in the IR.
    """

    allow_infinite: bool = False
    """
    Whether to allow using infinite registers during register allocation.
    """

    force_infinite: bool = False
    """
    Only use infinite registers during register allocation.
    """

    def apply(self, ctx: Context, op: ModuleOp) -> None:
        allocator_strategies = {
            "LivenessBlockNaive": RegisterAllocatorLivenessBlockNaive,
        }

        if self.allocation_strategy not in allocator_strategies:
            raise ValueError(
                f"Unknown register allocation strategy {self.allocation_strategy}. "
                f"Available allocation types: {allocator_strategies.keys()}"
            )

        for inner_op in op.walk():
            if isinstance(inner_op, riscv_func.FuncOp):
                register_stack = RiscvRegisterStack.get(
                    allow_infinite=self.allow_infinite | self.force_infinite,
                    allocatable_registers=() if self.force_infinite else None,
                )
                allocator = allocator_strategies[self.allocation_strategy](
                    register_stack
                )
                allocator.allocate_func(
                    inner_op, add_regalloc_stats=self.add_regalloc_stats
                )

name = 'riscv-allocate-registers' class-attribute instance-attribute

allocation_strategy: str = 'LivenessBlockNaive' class-attribute instance-attribute

add_regalloc_stats: bool = False class-attribute instance-attribute

Inserts a comment with register allocation info in the IR.

allow_infinite: bool = False class-attribute instance-attribute

Whether to allow using infinite registers during register allocation.

force_infinite: bool = False class-attribute instance-attribute

Only use infinite registers during register allocation.

__init__(allocation_strategy: str = 'LivenessBlockNaive', add_regalloc_stats: bool = False, allow_infinite: bool = False, force_infinite: bool = False) -> None

apply(ctx: Context, op: ModuleOp) -> None

Source code in xdsl/transforms/riscv_allocate_registers.py

def apply(self, ctx: Context, op: ModuleOp) -> None:
    allocator_strategies = {
        "LivenessBlockNaive": RegisterAllocatorLivenessBlockNaive,
    }

    if self.allocation_strategy not in allocator_strategies:
        raise ValueError(
            f"Unknown register allocation strategy {self.allocation_strategy}. "
            f"Available allocation types: {allocator_strategies.keys()}"
        )

    for inner_op in op.walk():
        if isinstance(inner_op, riscv_func.FuncOp):
            register_stack = RiscvRegisterStack.get(
                allow_infinite=self.allow_infinite | self.force_infinite,
                allocatable_registers=() if self.force_infinite else None,
            )
            allocator = allocator_strategies[self.allocation_strategy](
                register_stack
            )
            allocator.allocate_func(
                inner_op, add_regalloc_stats=self.add_regalloc_stats
            )