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145 | class X86Arch(Arch):
VECTOR_TYPES_BY_BITWIDTH: ClassVar[dict[int, type[X86VectorRegisterType]]] = {
128: SSERegisterType
}
"""
Supported vector type for a given vector size.
"""
@staticmethod
def name() -> str:
return "unknown"
@staticmethod
def arch_for_name(name: str | None) -> X86Arch:
if name is None:
return UNKNOWN
try:
return _ARCH_BY_NAME[name]
except KeyError:
raise DiagnosticException(f"Unsupported arch {name}")
def _register_type_for_vector_type(
self, value_type: VectorType
) -> type[X86VectorRegisterType]:
"""
Given any vector type, returns the appropriate register type.
The vector type must fit exactly into a full bitwidth vector supported by the
ISA, otherwise a `DiagnosticException` is raised.
"""
vector_num_elements = value_type.element_count()
element_type = cast(FixedBitwidthType, value_type.get_element_type())
element_size = element_type.bitwidth
vector_size = vector_num_elements * element_size
try:
return self.VECTOR_TYPES_BY_BITWIDTH[vector_size]
except KeyError:
raise DiagnosticException(
f"The vector size ({vector_size} bits) and target architecture `{self.name()}` are inconsistent."
)
def _scalar_type_for_type(self, value_type: Attribute) -> type[GeneralRegisterType]:
if isinstance(value_type, FixedBitwidthType):
match value_type.bitwidth:
case 64:
return Reg64Type
case 32:
return Reg32Type
case 16:
return Reg16Type
case 8:
return Reg8Type
case _:
...
if isinstance(value_type, IndexType) or isinstance(value_type, ptr.PtrType):
return Reg64Type
raise DiagnosticException(f"Register type for type {value_type} not supported.")
@overload
def register_type_for_type(
self, value_type: VectorType
) -> type[X86VectorRegisterType]: ...
@overload
def register_type_for_type(
self, value_type: Attribute
) -> type[X86RegisterType]: ...
def register_type_for_type(self, value_type: Attribute) -> type[X86RegisterType]:
if isinstance(value_type, X86RegisterType):
return type(value_type)
if isa(value_type, VectorType):
return self._register_type_for_vector_type(value_type)
return self._scalar_type_for_type(value_type)
def cast_to_regs(
self, values: Sequence[SSAValue], builder: Builder
) -> list[SSAValue]:
return [
builder.insert(
asm.ToRegOp.get(v, self.register_type_for_type(v.type).unallocated())
).register
for v in values
]
def move_value_to_unallocated(
self, value: SSAValue, value_type: Attribute, builder: Builder
) -> SSAValue:
if isa(value_type, VectorType[FixedBitwidthType]):
if not isinstance(reg_type := value.type, X86VectorRegisterType):
raise ValueError(f"Invalid type for move {value_type}")
# Choose the x86 vector instruction according to the
# abstract vector element size
match value_type.get_element_type().bitwidth:
case 16:
raise DiagnosticException(
"Half-precision floating point vector move is not implemented yet."
)
case 32:
raise DiagnosticException(
"Half-precision floating point vector move is not implemented yet."
)
case 64:
mov_op = x86.ops.DS_VmovapdOp(
value, destination=type(reg_type).unallocated()
)
case _:
raise DiagnosticException(
"Float precision must be half, single or double."
)
else:
if not isinstance(reg_type := value.type, GeneralRegisterType):
raise ValueError(f"Invalid type for move {value_type}")
mov_op = x86.DS_MovOp(value, destination=type(reg_type).unallocated())
return builder.insert_op(mov_op).results[0]
|