Ops

ops

The x86 dialect contains operations that represent x86 assembly operations.

In x86, the assembly operations may have different meaning depending on the types of arguments. For example, the mov instruction can assign an immediate value to a register, or move the contents of another register. In order to disambiguate the two, we use a mnemonic in the operation name to communicate which operands are expected, for example x86.ds.mov is the version that moves the contents of one register to another, and x86.di.mov is the version that sets the immediate value passed in to the register. The mnemonic encodes the types of the assembly instruction arguments, in order.

Here are the possible mnemonic values and what they stand for:

• s: Source register
• d: Destination register
• k: Mask register
• r: Register used both as a source and destination
• i: Immediate value
• m: Memory
• c: Condition

This dialect is structured into abstract base classes, which are prefixed with the mnemonic that corresponds to the subclassing operations (e.g. DS_Operation).

R1InvT = TypeVar('R1InvT', bound=X86RegisterType) module-attribute

R2InvT = TypeVar('R2InvT', bound=X86RegisterType) module-attribute

R3InvT = TypeVar('R3InvT', bound=X86RegisterType) module-attribute

R4InvT = TypeVar('R4InvT', bound=X86RegisterType) module-attribute

SI64: TypeAlias = IntegerType[Literal[64], Literal[Signedness.SIGNED]] module-attribute

SI32: TypeAlias = IntegerType[Literal[32], Literal[Signedness.SIGNED]] module-attribute

si64: SI64 = IntegerType(64, Signedness.SIGNED) module-attribute

si32: SI32 = IntegerType(32, Signedness.SIGNED) module-attribute

UI8: TypeAlias = IntegerType[Literal[8], Literal[Signedness.UNSIGNED]] module-attribute

ui8: UI8 = IntegerType(8, Signedness.UNSIGNED) module-attribute

X86AsmOperation dataclass

Bases: IRDLOperation, OneLineAssemblyPrintable, ABC

Base class for operations that can be a part of x86 assembly printing.

Source code in xdsl/dialects/x86/ops.py

class X86AsmOperation(IRDLOperation, OneLineAssemblyPrintable, ABC):
    """
    Base class for operations that can be a part of x86 assembly printing.
    """

X86RegisterAllocatableOperation dataclass

Bases: IRDLOperation, RegisterAllocatableOperation, ABC

Base class for x86 operations that can take part in register allocation.

Source code in xdsl/dialects/x86/ops.py

class X86RegisterAllocatableOperation(IRDLOperation, RegisterAllocatableOperation, ABC):
    """
    Base class for x86 operations that can take part in register allocation.
    """

X86HasRegisterConstraints dataclass

Bases: X86RegisterAllocatableOperation, HasRegisterConstraints, ABC

Base class for x86 operations with register constraints. By default, all operands are "in", and all results are "out", subclasses must override get_register_constraints if some of the results must be in the same registers as operands.

Source code in xdsl/dialects/x86/ops.py

class X86HasRegisterConstraints(
    X86RegisterAllocatableOperation, HasRegisterConstraints, ABC
):
    """
    Base class for x86 operations with register constraints.
    By default, all operands are "in", and all results are "out", subclasses must
    override `get_register_constraints` if some of the results must be in the same
    registers as operands.
    """

    def get_register_constraints(self) -> RegisterConstraints:
        # The default register constraints are that all operands are "in", and all
        # results are "out" registers.
        # If some registers are "inout" then this function must be overridden.
        return RegisterConstraints(self.operands, self.results, ())

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    # The default register constraints are that all operands are "in", and all
    # results are "out" registers.
    # If some registers are "inout" then this function must be overridden.
    return RegisterConstraints(self.operands, self.results, ())

X86CustomFormatOperation dataclass

Bases: IRDLOperation, ABC

Source code in xdsl/dialects/x86/ops.py

class X86CustomFormatOperation(IRDLOperation, ABC):
    @classmethod
    def parse(cls, parser: Parser) -> Self:
        args = cls.parse_unresolved_operands(parser)
        custom_attributes = cls.custom_parse_attributes(parser)
        remaining_attributes = parser.parse_optional_attr_dict()
        # TODO ensure distinct keys for attributes
        attributes = custom_attributes | remaining_attributes
        regions = parser.parse_region_list()
        pos = parser.pos
        operand_types, result_types = cls.parse_op_type(parser)
        operands = parser.resolve_operands(args, operand_types, pos)
        return cls.build(
            operands=operands,
            result_types=result_types,
            attributes=attributes,
            regions=regions,
        )

    @classmethod
    def parse_unresolved_operands(cls, parser: Parser) -> list[UnresolvedOperand]:
        """
        Parse a list of comma separated unresolved operands.
        Notice that this method will consume trailing comma.
        """
        if operand := parser.parse_optional_unresolved_operand():
            operands = [operand]
            while parser.parse_optional_punctuation(",") and (
                operand := parser.parse_optional_unresolved_operand()
            ):
                operands.append(operand)
            return operands
        return []

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        """
        Parse attributes with custom syntax. Subclasses may override this method.
        """
        return parser.parse_optional_attr_dict()

    @classmethod
    def parse_op_type(
        cls, parser: Parser
    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
        parser.parse_punctuation(":")
        func_type = parser.parse_function_type()
        return func_type.inputs.data, func_type.outputs.data

    def print(self, printer: Printer) -> None:
        if self.operands:
            printer.print_string(" ")
            printer.print_list(self.operands, printer.print_operand)
        printed_attributes = self.custom_print_attributes(printer)
        unprinted_attributes = {
            name: attr
            for name, attr in self.attributes.items()
            if name not in printed_attributes
        }
        printer.print_op_attributes(unprinted_attributes)
        printer.print_regions(self.regions)
        self.print_op_type(printer)

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        """
        Print attributes with custom syntax. Return the names of the attributes printed. Subclasses may override this method.
        """
        printer.print_op_attributes(self.attributes)
        return self.attributes.keys()

    def print_op_type(self, printer: Printer) -> None:
        printer.print_string(" : ")
        printer.print_operation_type(self)

parse(parser: Parser) -> Self classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse(cls, parser: Parser) -> Self:
    args = cls.parse_unresolved_operands(parser)
    custom_attributes = cls.custom_parse_attributes(parser)
    remaining_attributes = parser.parse_optional_attr_dict()
    # TODO ensure distinct keys for attributes
    attributes = custom_attributes | remaining_attributes
    regions = parser.parse_region_list()
    pos = parser.pos
    operand_types, result_types = cls.parse_op_type(parser)
    operands = parser.resolve_operands(args, operand_types, pos)
    return cls.build(
        operands=operands,
        result_types=result_types,
        attributes=attributes,
        regions=regions,
    )

parse_unresolved_operands(parser: Parser) -> list[UnresolvedOperand] classmethod

Parse a list of comma separated unresolved operands. Notice that this method will consume trailing comma.

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse_unresolved_operands(cls, parser: Parser) -> list[UnresolvedOperand]:
    """
    Parse a list of comma separated unresolved operands.
    Notice that this method will consume trailing comma.
    """
    if operand := parser.parse_optional_unresolved_operand():
        operands = [operand]
        while parser.parse_optional_punctuation(",") and (
            operand := parser.parse_optional_unresolved_operand()
        ):
            operands.append(operand)
        return operands
    return []

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Parse attributes with custom syntax. Subclasses may override this method.

Source code in xdsl/dialects/x86/ops.py

@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    """
    Parse attributes with custom syntax. Subclasses may override this method.
    """
    return parser.parse_optional_attr_dict()

parse_op_type(parser: Parser) -> tuple[Sequence[Attribute], Sequence[Attribute]] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse_op_type(
    cls, parser: Parser
) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
    parser.parse_punctuation(":")
    func_type = parser.parse_function_type()
    return func_type.inputs.data, func_type.outputs.data

print(printer: Printer) -> None

Source code in xdsl/dialects/x86/ops.py

def print(self, printer: Printer) -> None:
    if self.operands:
        printer.print_string(" ")
        printer.print_list(self.operands, printer.print_operand)
    printed_attributes = self.custom_print_attributes(printer)
    unprinted_attributes = {
        name: attr
        for name, attr in self.attributes.items()
        if name not in printed_attributes
    }
    printer.print_op_attributes(unprinted_attributes)
    printer.print_regions(self.regions)
    self.print_op_type(printer)

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Print attributes with custom syntax. Return the names of the attributes printed. Subclasses may override this method.

Source code in xdsl/dialects/x86/ops.py

def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    """
    Print attributes with custom syntax. Return the names of the attributes printed. Subclasses may override this method.
    """
    printer.print_op_attributes(self.attributes)
    return self.attributes.keys()

print_op_type(printer: Printer) -> None

Source code in xdsl/dialects/x86/ops.py

def print_op_type(self, printer: Printer) -> None:
    printer.print_string(" : ")
    printer.print_operation_type(self)

X86Instruction dataclass

Bases: X86AsmOperation, X86HasRegisterConstraints

Base class for operations that can be a part of x86 assembly printing. Must represent an instruction in the x86 instruction set. The name of the operation will be used as the x86 assembly instruction name.

Source code in xdsl/dialects/x86/ops.py

class X86Instruction(X86AsmOperation, X86HasRegisterConstraints):
    """
    Base class for operations that can be a part of x86 assembly printing. Must
    represent an instruction in the x86 instruction set.
    The name of the operation will be used as the x86 assembly instruction name.
    """

    traits = traits_def(RegisterAllocatedMemoryEffect())

    comment = opt_attr_def(StringAttr)
    """
    An optional comment that will be printed along with the instruction.
    """

    @abstractmethod
    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        """
        The arguments to the instruction, in the order they should be printed in the
        assembly.
        """
        raise NotImplementedError()

    def assembly_instruction_name(self) -> str:
        """
        By default, the name of the instruction is the same as the name of the operation.
        """

        return self.name.split(".")[-1]

    def assembly_line(self) -> str | None:
        # default assembly code generator
        instruction_name = self.assembly_instruction_name()
        arg_str = ", ".join(
            assembly_arg_str(arg)
            for arg in self.assembly_line_args()
            if arg is not None
        )
        return AssemblyPrinter.assembly_line(instruction_name, arg_str, self.comment)

traits = traits_def(RegisterAllocatedMemoryEffect()) class-attribute instance-attribute

comment = opt_attr_def(StringAttr) class-attribute instance-attribute

An optional comment that will be printed along with the instruction.

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...] abstractmethod

The arguments to the instruction, in the order they should be printed in the assembly.

Source code in xdsl/dialects/x86/ops.py

@abstractmethod
def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    """
    The arguments to the instruction, in the order they should be printed in the
    assembly.
    """
    raise NotImplementedError()

assembly_instruction_name() -> str

By default, the name of the instruction is the same as the name of the operation.

Source code in xdsl/dialects/x86/ops.py

def assembly_instruction_name(self) -> str:
    """
    By default, the name of the instruction is the same as the name of the operation.
    """

    return self.name.split(".")[-1]

assembly_line() -> str | None

Source code in xdsl/dialects/x86/ops.py

def assembly_line(self) -> str | None:
    # default assembly code generator
    instruction_name = self.assembly_instruction_name()
    arg_str = ", ".join(
        assembly_arg_str(arg)
        for arg in self.assembly_line_args()
        if arg is not None
    )
    return AssemblyPrinter.assembly_line(instruction_name, arg_str, self.comment)

RS_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that have one register that is read and written to, and one source register.

Source code in xdsl/dialects/x86/ops.py

class RS_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that have one register that is read and written to,
    and one source register.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)

    source = operand_def(R2InvT)

    assembly_format = (
        "$register_in `,` $source attr-dict `:` "
        "`(` type($register_in) `,` type($source) `)` `->` type($register_out)"
    )

    def __init__(
        self,
        register_in: Operation | SSAValue,
        source: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        register_in = SSAValue.get(register_in)
        if register_out is None:
            register_out = cast(R1InvT, register_in.type)

        super().__init__(
            operands=[register_in, source],
            attributes={
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.register_in), reg(self.source)

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.source,), (), ((self.register_in, self.register_out),)
        )

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

assembly_format = '$register_in `,` $source attr-dict `:` `(` type($register_in) `,` type($source) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: Operation | SSAValue, source: Operation | SSAValue, *, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: Operation | SSAValue,
    source: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    register_in = SSAValue.get(register_in)
    if register_out is None:
        register_out = cast(R1InvT, register_in.type)

    super().__init__(
        operands=[register_in, source],
        attributes={
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.register_in), reg(self.source)

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.source,), (), ((self.register_in, self.register_out),)
    )

DS_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that have one destination register and one source register.

Source code in xdsl/dialects/x86/ops.py

class DS_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that have one destination register and one source
    register.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    source = operand_def(R2InvT)

    assembly_format = (
        "$source attr-dict `:` `(` type($source) `)` `->` type($destination)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source],
            attributes={
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (reg(self.destination), reg(self.source))

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

assembly_format = '$source attr-dict `:` `(` type($source) `)` `->` type($destination)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source],
        attributes={
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (reg(self.destination), reg(self.source))

DSK_Operation

Bases: X86Instruction, ABC

A base class for x86 operations that have one destination register and one source register.

Source code in xdsl/dialects/x86/ops.py

class DSK_Operation(X86Instruction, ABC):
    """
    A base class for x86 operations that have one destination register and one source
    register.
    """

    destination: OpResult[X86VectorRegisterType] = result_def(X86VectorRegisterType)
    source = operand_def(X86VectorRegisterType)
    mask_reg = operand_def(AVX512MaskRegisterType)
    z = opt_attr_def(UnitAttr)

    assembly_format = (
        "$source `,` $mask_reg attr-dict `:` "
        "`(` type($source) `,` type($mask_reg) `)` `->` type($destination)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        mask_reg: Operation | SSAValue,
        *,
        z: bool = False,
        comment: str | StringAttr | None = None,
        destination: X86VectorRegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source, mask_reg],
            attributes={
                "z": UnitAttr() if z else None,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        register_out = masked_source_str(self.destination, self.mask_reg, self.z)
        return register_out, reg(self.source)

destination: OpResult[X86VectorRegisterType] = result_def(X86VectorRegisterType) class-attribute instance-attribute

source = operand_def(X86VectorRegisterType) class-attribute instance-attribute

mask_reg = operand_def(AVX512MaskRegisterType) class-attribute instance-attribute

z = opt_attr_def(UnitAttr) class-attribute instance-attribute

assembly_format = '$source `,` $mask_reg attr-dict `:` `(` type($source) `,` type($mask_reg) `)` `->` type($destination)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, mask_reg: Operation | SSAValue, *, z: bool = False, comment: str | StringAttr | None = None, destination: X86VectorRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    mask_reg: Operation | SSAValue,
    *,
    z: bool = False,
    comment: str | StringAttr | None = None,
    destination: X86VectorRegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source, mask_reg],
        attributes={
            "z": UnitAttr() if z else None,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    register_out = masked_source_str(self.destination, self.mask_reg, self.z)
    return register_out, reg(self.source)

DK_Operation

Bases: X86Instruction, X86CustomFormatOperation, HasRegisterConstraints, ABC

A base class for x86 operations that have one general purpose destination register and one writemask source register.

Source code in xdsl/dialects/x86/ops.py

class DK_Operation(
    X86Instruction, X86CustomFormatOperation, HasRegisterConstraints, ABC
):
    """
    A base class for x86 operations that have one general purpose destination register
    and one writemask source register.
    """

    destination: OpResult[GeneralRegisterType] = result_def(GeneralRegisterType)
    source = operand_def(AVX512MaskRegisterType)

    def __init__(
        self,
        source: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        destination: GeneralRegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=(source,),
            attributes={
                "comment": comment,
            },
            result_types=(destination,),
        )

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints((self.source,), (self.destination,), ())

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.destination), reg(self.source)

destination: OpResult[GeneralRegisterType] = result_def(GeneralRegisterType) class-attribute instance-attribute

source = operand_def(AVX512MaskRegisterType) class-attribute instance-attribute

__init__(source: Operation | SSAValue, *, comment: str | StringAttr | None = None, destination: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    destination: GeneralRegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=(source,),
        attributes={
            "comment": comment,
        },
        result_types=(destination,),
    )

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints((self.source,), (self.destination,), ())

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.destination), reg(self.source)

KS_Operation

Bases: X86Instruction, X86CustomFormatOperation, HasRegisterConstraints, ABC

A base class for x86 operations that have one general purpose destination register and one writemask source register.

Source code in xdsl/dialects/x86/ops.py

class KS_Operation(
    X86Instruction, X86CustomFormatOperation, HasRegisterConstraints, ABC
):
    """
    A base class for x86 operations that have one general purpose destination register
    and one writemask source register.
    """

    destination: OpResult[AVX512MaskRegisterType] = result_def(AVX512MaskRegisterType)
    source = operand_def(GeneralRegisterType)

    def __init__(
        self,
        source: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        destination: AVX512MaskRegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=(source,),
            attributes={
                "comment": comment,
            },
            result_types=(destination,),
        )

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints((self.source,), (self.destination,), ())

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.destination), reg(self.source)

destination: OpResult[AVX512MaskRegisterType] = result_def(AVX512MaskRegisterType) class-attribute instance-attribute

source = operand_def(GeneralRegisterType) class-attribute instance-attribute

__init__(source: Operation | SSAValue, *, comment: str | StringAttr | None = None, destination: AVX512MaskRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    destination: AVX512MaskRegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=(source,),
        attributes={
            "comment": comment,
        },
        result_types=(destination,),
    )

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints((self.source,), (self.destination,), ())

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.destination), reg(self.source)

R_Operation

Bases: X86Instruction, ABC, Generic[R1InvT]

A base class for x86 operations that have one register that is read and written to.

Source code in xdsl/dialects/x86/ops.py

class R_Operation(X86Instruction, ABC, Generic[R1InvT]):
    """
    A base class for x86 operations that have one register that is read and written to.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)

    assembly_format = (
        "$register_in attr-dict `:` `(` type($register_in) `)` `->` type($register_out)"
    )

    def __init__(
        self,
        register_in: SSAValue[R1InvT],
        *,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        if register_out is None:
            register_out = register_in.type
        super().__init__(
            operands=[register_in],
            attributes={
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (reg(self.register_in),)

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints((), (), ((self.register_in, self.register_out),))

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

assembly_format = '$register_in attr-dict `:` `(` type($register_in) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: SSAValue[R1InvT], *, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: SSAValue[R1InvT],
    *,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    if register_out is None:
        register_out = register_in.type
    super().__init__(
        operands=[register_in],
        attributes={
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (reg(self.register_in),)

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints((), (), ((self.register_in, self.register_out),))

RM_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that have one register read and written to and one memory access with an optional offset.

Source code in xdsl/dialects/x86/ops.py

class RM_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that have one register read and written to and one
    memory access with an optional offset.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)

    memory = operand_def(R2InvT)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "$register_in `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($register_in) `,` type($memory) `)` `->` type($register_out)"
    )

    def __init__(
        self,
        register_in: Operation | SSAValue,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[I64],
        *,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)
        register_in = SSAValue.get(register_in)
        if register_out is None:
            register_out = cast(R1InvT, register_in.type)

        super().__init__(
            operands=[register_in, memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        destination = assembly_arg_str(reg(self.register_in))
        return (destination, memory_access)

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.memory,), (), ((self.register_in, self.register_out),)
        )

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

memory = operand_def(R2InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '$register_in `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($register_in) `,` type($memory) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: Operation | SSAValue, memory: Operation | SSAValue, memory_offset: int | IntegerAttr[I64], *, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: Operation | SSAValue,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[I64],
    *,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)
    register_in = SSAValue.get(register_in)
    if register_out is None:
        register_out = cast(R1InvT, register_in.type)

    super().__init__(
        operands=[register_in, memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    destination = assembly_arg_str(reg(self.register_in))
    return (destination, memory_access)

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.memory,), (), ((self.register_in, self.register_out),)
    )

DM_OperationHasCanonicalizationPatterns dataclass

Bases: HasCanonicalizationPatternsTrait

Source code in xdsl/dialects/x86/ops.py

class DM_OperationHasCanonicalizationPatterns(HasCanonicalizationPatternsTrait):
    @classmethod
    def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
        from xdsl.transforms.canonicalization_patterns.x86 import (
            DM_Operation_ConstantOffset,
        )

        return (DM_Operation_ConstantOffset(),)

get_canonicalization_patterns() -> tuple[RewritePattern, ...] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
    from xdsl.transforms.canonicalization_patterns.x86 import (
        DM_Operation_ConstantOffset,
    )

    return (DM_Operation_ConstantOffset(),)

DM_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that load from memory into a destination register.

Source code in xdsl/dialects/x86/ops.py

class DM_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that load from memory into a destination register.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    memory = operand_def(R2InvT)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))

    traits = traits_def(
        DM_OperationHasCanonicalizationPatterns(),
        MemoryReadEffect(),
    )

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "functional-type($memory, $destination)"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)
        super().__init__(
            operands=[memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        destination = assembly_arg_str(reg(self.destination))
        return (destination, memory_access)

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

memory = operand_def(R2InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

traits = traits_def(DM_OperationHasCanonicalizationPatterns(), MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` functional-type($memory, $destination)' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, memory_offset: int | IntegerAttr, *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)
    super().__init__(
        operands=[memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    destination = assembly_arg_str(reg(self.destination))
    return (destination, memory_access)

DMK_Operation

Bases: X86Instruction, ABC, Generic[R1InvT]

A base class for x86 AVX512 operations that have one destination register d that is written to, a source register m that contains a pointer, a constant offset, and a mask register k. The z attribute enables zero masking, which sets the elements of the destination register to zero where the corresponding bit in the mask is zero.

Source code in xdsl/dialects/x86/ops.py

class DMK_Operation(X86Instruction, ABC, Generic[R1InvT]):
    """
    A base class for x86 AVX512 operations that have one destination register d that is
    written to, a source register m that contains a pointer, a constant offset, and a
    mask register k. The z attribute enables zero masking, which sets the elements of
    the destination register to zero where the corresponding bit in the mask is zero.
    """

    destination = result_def(X86VectorRegisterType)
    memory = operand_def(R1InvT)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))
    mask_reg = operand_def(AVX512MaskRegisterType)
    z = opt_attr_def(UnitAttr)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "`[` $memory (`+` $memory_offset^)? `]` `,` $mask_reg attr-dict `:` "
        "`(` type($memory) `,` type($mask_reg) `)` `->` type($destination)"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        mask_reg: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        z: bool = False,
        comment: str | StringAttr | None = None,
        destination: X86VectorRegisterType,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=(memory, mask_reg),
            attributes={
                "memory_offset": memory_offset,
                "z": UnitAttr() if z else None,
                "comment": comment,
            },
            result_types=(destination,),
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        destination = masked_source_str(self.destination, self.mask_reg, self.z)
        return (destination, memory_access)

destination = result_def(X86VectorRegisterType) class-attribute instance-attribute

memory = operand_def(R1InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

mask_reg = operand_def(AVX512MaskRegisterType) class-attribute instance-attribute

z = opt_attr_def(UnitAttr) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '`[` $memory (`+` $memory_offset^)? `]` `,` $mask_reg attr-dict `:` `(` type($memory) `,` type($mask_reg) `)` `->` type($destination)' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, mask_reg: Operation | SSAValue, memory_offset: int | IntegerAttr, *, z: bool = False, comment: str | StringAttr | None = None, destination: X86VectorRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    mask_reg: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    z: bool = False,
    comment: str | StringAttr | None = None,
    destination: X86VectorRegisterType,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=(memory, mask_reg),
        attributes={
            "memory_offset": memory_offset,
            "z": UnitAttr() if z else None,
            "comment": comment,
        },
        result_types=(destination,),
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    destination = masked_source_str(self.destination, self.mask_reg, self.z)
    return (destination, memory_access)

DI_Operation

Bases: X86Instruction, ABC, Generic[R1InvT]

A base class for x86 operations that have one destination register and an immediate value.

Source code in xdsl/dialects/x86/ops.py

class DI_Operation(X86Instruction, ABC, Generic[R1InvT]):
    """
    A base class for x86 operations that have one destination register and an immediate
    value.
    """

    # In the future, we should look into the legal bitwidths in the binary
    # representation.
    immediate = attr_def(IntegerAttr[SI32])
    destination: OpResult[R1InvT] = result_def(R1InvT)

    assembly_format = "$immediate attr-dict `:` `(` `)` `->` type($destination)"

    def __init__(
        self,
        immediate: int | IntegerAttr[SI32],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.destination), self.immediate

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

assembly_format = '$immediate attr-dict `:` `(` `)` `->` type($destination)' class-attribute instance-attribute

__init__(immediate: int | IntegerAttr[SI32], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    immediate: int | IntegerAttr[SI32],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.destination), self.immediate

RI_Operation

Bases: X86Instruction, ABC, Generic[R1InvT]

A base class for x86 operations that have one register that is read and written to and an immediate value.

Source code in xdsl/dialects/x86/ops.py

class RI_Operation(X86Instruction, ABC, Generic[R1InvT]):
    """
    A base class for x86 operations that have one register that is read and written to
    and an immediate value.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)

    # In the future, we should look into the legal bitwidths in the binary
    # representation.
    immediate = attr_def(IntegerAttr[SI32])

    assembly_format = (
        "$register_in `,` $immediate attr-dict `:` "
        "`(` type($register_in) `)` `->` type($register_out)"
    )

    def __init__(
        self,
        register_in: Operation | SSAValue,
        immediate: int | IntegerAttr[SI32],
        *,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(comment, str):
            comment = StringAttr(comment)
        register_in = SSAValue.get(register_in)
        if register_out is None:
            register_out = cast(R1InvT, register_in.type)

        super().__init__(
            operands=[register_in],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.register_in), self.immediate

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints((), (), ((self.register_in, self.register_out),))

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

assembly_format = '$register_in `,` $immediate attr-dict `:` `(` type($register_in) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: Operation | SSAValue, immediate: int | IntegerAttr[SI32], *, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: Operation | SSAValue,
    immediate: int | IntegerAttr[SI32],
    *,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(comment, str):
        comment = StringAttr(comment)
    register_in = SSAValue.get(register_in)
    if register_out is None:
        register_out = cast(R1InvT, register_in.type)

    super().__init__(
        operands=[register_in],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.register_in), self.immediate

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints((), (), ((self.register_in, self.register_out),))

MS_OperationHasCanonicalizationPatterns dataclass

Bases: HasCanonicalizationPatternsTrait

Source code in xdsl/dialects/x86/ops.py

class MS_OperationHasCanonicalizationPatterns(HasCanonicalizationPatternsTrait):
    @classmethod
    def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
        from xdsl.transforms.canonicalization_patterns.x86 import (
            MS_Operation_ConstantOffset,
        )

        return (MS_Operation_ConstantOffset(),)

get_canonicalization_patterns() -> tuple[RewritePattern, ...] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
    from xdsl.transforms.canonicalization_patterns.x86 import (
        MS_Operation_ConstantOffset,
    )

    return (MS_Operation_ConstantOffset(),)

MS_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that write one source register to a memory destination. Read-modify-write subclasses must additionally declare a memory read.

Source code in xdsl/dialects/x86/ops.py

class MS_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that write one source register to a memory
    destination. Read-modify-write subclasses must additionally declare a memory read.
    """

    memory = operand_def(R1InvT)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))
    source = operand_def(R2InvT)

    traits = traits_def(
        MS_OperationHasCanonicalizationPatterns(),
        MemoryWriteEffect(),
    )

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $source attr-dict `:` "
        "`(` type($memory) `,` type($source) `)` `->` `(` `)`"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        source: Operation | SSAValue,
        memory_offset: int | IntegerAttr[I64],
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory, source],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return memory_access, reg(self.source)

memory = operand_def(R1InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

traits = traits_def(MS_OperationHasCanonicalizationPatterns(), MemoryWriteEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $source attr-dict `:` `(` type($memory) `,` type($source) `)` `->` `(` `)`' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, source: Operation | SSAValue, memory_offset: int | IntegerAttr[I64], *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    source: Operation | SSAValue,
    memory_offset: int | IntegerAttr[I64],
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory, source],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return memory_access, reg(self.source)

MSK_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 AVX512 operations that have one destination register that is written to, a memory operand (with optional offset), a source register, and a mask register. The z attribute enables zero-masking, which sets the elements of the destination register to zero where the mask is zero.

Typical usage: [m+offset]{k} := s where [m+offset] is the memory location addressed by the base register and offset, s is the source vector register, and k is the mask.

Source code in xdsl/dialects/x86/ops.py

class MSK_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 AVX512 operations that have one destination register that is
    written to, a memory operand (with optional offset), a source register, and a mask
    register. The z attribute enables zero-masking, which sets the elements of the
    destination register to zero where the mask is zero.

    Typical usage: [m+offset]{k} := s
    where [m+offset] is the memory location addressed by the base register and offset,
    s is the source vector register, and k is the mask.
    """

    memory = operand_def(R1InvT)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))
    source = operand_def(R2InvT)
    mask_reg = operand_def(AVX512MaskRegisterType)
    z = opt_attr_def(UnitAttr)

    traits = traits_def(MemoryWriteEffect())

    assembly_format = (
        "`[` $memory (`+` $memory_offset^)? `]` `,` $source `,` $mask_reg attr-dict `:` "
        "`(` type($memory) `,` type($source) `,` type($mask_reg) `)` `->` `(` `)`"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        source: Operation | SSAValue,
        mask_reg: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        z: bool = False,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory, source, mask_reg],
            attributes={
                "memory_offset": memory_offset,
                "z": UnitAttr() if z else None,
                "comment": comment,
            },
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        masked_mem = masked_memory_access_str(
            self.memory, self.memory_offset, self.mask_reg, self.z
        )
        return (masked_mem, reg(self.source))

memory = operand_def(R1InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

mask_reg = operand_def(AVX512MaskRegisterType) class-attribute instance-attribute

z = opt_attr_def(UnitAttr) class-attribute instance-attribute

traits = traits_def(MemoryWriteEffect()) class-attribute instance-attribute

assembly_format = '`[` $memory (`+` $memory_offset^)? `]` `,` $source `,` $mask_reg attr-dict `:` `(` type($memory) `,` type($source) `,` type($mask_reg) `)` `->` `(` `)`' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, source: Operation | SSAValue, mask_reg: Operation | SSAValue, memory_offset: int | IntegerAttr, *, z: bool = False, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    source: Operation | SSAValue,
    mask_reg: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    z: bool = False,
    comment: str | StringAttr | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory, source, mask_reg],
        attributes={
            "memory_offset": memory_offset,
            "z": UnitAttr() if z else None,
            "comment": comment,
        },
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    masked_mem = masked_memory_access_str(
        self.memory, self.memory_offset, self.mask_reg, self.z
    )
    return (masked_mem, reg(self.source))

MI_Operation

Bases: X86Instruction, ABC, Generic[R1InvT]

A base class for x86 operations that have one memory reference and an immediate value.

Source code in xdsl/dialects/x86/ops.py

class MI_Operation(X86Instruction, ABC, Generic[R1InvT]):
    """
    A base class for x86 operations that have one memory reference and an immediate
    value.
    """

    memory = operand_def(R1InvT)
    # In the future, we should look into the legal bitwidths in the binary
    # representation.
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))
    immediate = attr_def(IntegerAttr[SI32])

    traits = traits_def(MemoryReadEffect(), MemoryWriteEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $immediate attr-dict `:` "
        "`(` type($memory) `)` `->` `(` `)`"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[SI64],
        immediate: int | IntegerAttr[SI32],
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory],
            attributes={
                "immediate": immediate,
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        immediate = assembly_arg_str(self.immediate)
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return memory_access, immediate

memory = operand_def(R1InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect(), MemoryWriteEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $immediate attr-dict `:` `(` type($memory) `)` `->` `(` `)`' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, memory_offset: int | IntegerAttr[SI64], immediate: int | IntegerAttr[SI32], *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[SI64],
    immediate: int | IntegerAttr[SI32],
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory],
        attributes={
            "immediate": immediate,
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    immediate = assembly_arg_str(self.immediate)
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return memory_access, immediate

DSI_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that have one destination register, one source register and an immediate value.

Source code in xdsl/dialects/x86/ops.py

class DSI_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that have one destination register, one source
    register and an immediate value.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    source = operand_def(R2InvT)
    # In the future, we should look into the legal bitwidths in the binary
    # representation.
    immediate = attr_def(IntegerAttr[SI32])

    assembly_format = (
        "$source `,` $immediate attr-dict `:` "
        "`(` type($source) `)` `->` type($destination)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        immediate: int | IntegerAttr[SI32],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.destination), reg(self.source), self.immediate

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

assembly_format = '$source `,` $immediate attr-dict `:` `(` type($source) `)` `->` type($destination)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, immediate: int | IntegerAttr[SI32], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    immediate: int | IntegerAttr[SI32],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.destination), reg(self.source), self.immediate

DSI8_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that have one destination register, one source register, and an unsigned 8-bit immediate value.

Source code in xdsl/dialects/x86/ops.py

class DSI8_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that have one destination register, one source
    register, and an unsigned 8-bit immediate value.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    source = operand_def(R2InvT)
    immediate = prop_def(IntegerAttr[UI8])

    assembly_format = (
        "$source `,` $immediate attr-dict `:` functional-type($source, $destination)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        immediate: int | IntegerAttr[UI8],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, ui8)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source],
            attributes={
                "comment": comment,
            },
            properties={
                "immediate": immediate,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.destination), reg(self.source), self.immediate

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

immediate = prop_def(IntegerAttr[UI8]) class-attribute instance-attribute

assembly_format = '$source `,` $immediate attr-dict `:` functional-type($source, $destination)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, immediate: int | IntegerAttr[UI8], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    immediate: int | IntegerAttr[UI8],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, ui8)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source],
        attributes={
            "comment": comment,
        },
        properties={
            "immediate": immediate,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.destination), reg(self.source), self.immediate

DMI_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT]

A base class for x86 operations that have one destination register, one memory reference and an immediate value.

Source code in xdsl/dialects/x86/ops.py

class DMI_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT]):
    """
    A base class for x86 operations that have one destination register, one memory
    reference and an immediate value.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    memory = operand_def(R2InvT)
    # In the future, we should look into the legal bitwidths in the binary
    # representation.
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))
    immediate = attr_def(IntegerAttr[SI32])
    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $immediate attr-dict `:` "
        "`(` type($memory) `)` `->` type($destination)"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        immediate: int | IntegerAttr[SI32],
        memory_offset: int | IntegerAttr[SI64],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory],
            attributes={
                "immediate": immediate,
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        destination = assembly_arg_str(reg(self.destination))
        immediate = assembly_arg_str(self.immediate)
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return destination, memory_access, immediate

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

memory = operand_def(R2InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $immediate attr-dict `:` `(` type($memory) `)` `->` type($destination)' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, immediate: int | IntegerAttr[SI32], memory_offset: int | IntegerAttr[SI64], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    immediate: int | IntegerAttr[SI32],
    memory_offset: int | IntegerAttr[SI64],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory],
        attributes={
            "immediate": immediate,
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    destination = assembly_arg_str(reg(self.destination))
    immediate = assembly_arg_str(self.immediate)
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return destination, memory_access, immediate

M_Operation

Bases: X86Instruction, ABC, Generic[R1InvT]

A base class for x86 operations with a memory reference.

Source code in xdsl/dialects/x86/ops.py

class M_Operation(X86Instruction, ABC, Generic[R1InvT]):
    """
    A base class for x86 operations with a memory reference.
    """

    memory = operand_def(R1InvT)
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))
    traits = traits_def(MemoryWriteEffect(), MemoryReadEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($memory) `)` `->` `(` `)`"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[SI64],
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)

        super().__init__(
            operands=[memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return (memory_access,)

memory = operand_def(R1InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

traits = traits_def(MemoryWriteEffect(), MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($memory) `)` `->` `(` `)`' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, memory_offset: int | IntegerAttr[SI64], *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[SI64],
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)

    super().__init__(
        operands=[memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return (memory_access,)

ConditionalJumpOperation

Bases: X86Instruction, X86CustomFormatOperation, ABC

A base class for Jcc operations.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

class ConditionalJumpOperation(X86Instruction, X86CustomFormatOperation, ABC):
    """
    A base class for Jcc operations.

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    rflags = operand_def(RFLAGS)

    then_values = var_operand_def(X86RegisterType)
    else_values = var_operand_def(X86RegisterType)

    irdl_options = (AttrSizedOperandSegments(),)

    then_block = successor_def()
    else_block = successor_def()

    traits = traits_def(IsTerminator())

    def __init__(
        self,
        rflags: Operation | SSAValue,
        then_values: Sequence[SSAValue],
        else_values: Sequence[SSAValue],
        then_block: Successor,
        else_block: Successor,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rflags, then_values, else_values],
            attributes={
                "comment": comment,
            },
            successors=(then_block, else_block),
        )

    def verify_(self) -> None:
        # The then block must start with a label op

        then_block_first_op = self.then_block.first_op

        if not isinstance(then_block_first_op, LabelOp):
            raise VerifyException("then block first op must be a label")

        # Types of arguments must match arg types of blocks

        for op_arg, block_arg in zip(self.then_values, self.then_block.args):
            if op_arg.type != block_arg.type:
                raise VerifyException(
                    f"Block arg types must match {op_arg.type} {block_arg.type}"
                )

        for op_arg, block_arg in zip(self.else_values, self.else_block.args):
            if op_arg.type != block_arg.type:
                raise VerifyException(
                    f"Block arg types must match {op_arg.type} {block_arg.type}"
                )

        # The else block must be the one immediately following this one

        parent_block = self.parent
        if parent_block is None:
            return

        parent_region = parent_block.parent
        if parent_region is None:
            return

        if parent_block.next_block is not self.else_block:
            raise VerifyException("else block must be immediately after op")

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        then_label = self.then_block.first_op
        assert isinstance(then_label, LabelOp)
        then_label_str = then_label.label.data
        if then_label_str.isdigit():
            # x86 Assembly: Numeric jump labels must be annotated with a suffix.
            # Jumping backward in code requires appending 'b' (e.g., "1b"), and
            # jumping forward requires appending 'f' (e.g., "1f").
            # Proper support for generating these labels is currently unimplemented.
            raise NotImplementedError(
                "Assembly printing for jumps to numeric labels not implemented"
            )
        return (then_label_str,)

    def print(self, printer: Printer) -> None:
        printer.print_string(" ")
        print_type_pair(printer, self.rflags)
        printer.print_string(", ")
        printer.print_block_name(self.then_block)
        printer.print_string("(")
        printer.print_list(self.then_values, lambda val: print_type_pair(printer, val))
        printer.print_string("), ")
        printer.print_block_name(self.else_block)
        printer.print_string("(")
        printer.print_list(self.else_values, lambda val: print_type_pair(printer, val))
        printer.print_string(")")
        if self.attributes:
            printer.print_op_attributes(
                self.attributes,
                reserved_attr_names="operandSegmentSizes",
                print_keyword=True,
            )

    @classmethod
    def parse(cls, parser: Parser) -> Self:
        rflags = parse_type_pair(parser)
        parser.parse_punctuation(",")
        then_block = parser.parse_successor()
        then_args = parser.parse_comma_separated_list(
            parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
        )
        parser.parse_punctuation(",")
        else_block = parser.parse_successor()
        else_args = parser.parse_comma_separated_list(
            parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
        )
        attrs = parser.parse_optional_attr_dict_with_keyword()
        op = cls(rflags, then_args, else_args, then_block, else_block)
        if attrs is not None:
            op.attributes |= attrs.data
        return op

rflags = operand_def(RFLAGS) class-attribute instance-attribute

then_values = var_operand_def(X86RegisterType) class-attribute instance-attribute

else_values = var_operand_def(X86RegisterType) class-attribute instance-attribute

irdl_options = (AttrSizedOperandSegments(),) class-attribute instance-attribute

then_block = successor_def() class-attribute instance-attribute

else_block = successor_def() class-attribute instance-attribute

traits = traits_def(IsTerminator()) class-attribute instance-attribute

__init__(rflags: Operation | SSAValue, then_values: Sequence[SSAValue], else_values: Sequence[SSAValue], then_block: Successor, else_block: Successor, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    rflags: Operation | SSAValue,
    then_values: Sequence[SSAValue],
    else_values: Sequence[SSAValue],
    then_block: Successor,
    else_block: Successor,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rflags, then_values, else_values],
        attributes={
            "comment": comment,
        },
        successors=(then_block, else_block),
    )

verify_() -> None

Source code in xdsl/dialects/x86/ops.py

def verify_(self) -> None:
    # The then block must start with a label op

    then_block_first_op = self.then_block.first_op

    if not isinstance(then_block_first_op, LabelOp):
        raise VerifyException("then block first op must be a label")

    # Types of arguments must match arg types of blocks

    for op_arg, block_arg in zip(self.then_values, self.then_block.args):
        if op_arg.type != block_arg.type:
            raise VerifyException(
                f"Block arg types must match {op_arg.type} {block_arg.type}"
            )

    for op_arg, block_arg in zip(self.else_values, self.else_block.args):
        if op_arg.type != block_arg.type:
            raise VerifyException(
                f"Block arg types must match {op_arg.type} {block_arg.type}"
            )

    # The else block must be the one immediately following this one

    parent_block = self.parent
    if parent_block is None:
        return

    parent_region = parent_block.parent
    if parent_region is None:
        return

    if parent_block.next_block is not self.else_block:
        raise VerifyException("else block must be immediately after op")

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    then_label = self.then_block.first_op
    assert isinstance(then_label, LabelOp)
    then_label_str = then_label.label.data
    if then_label_str.isdigit():
        # x86 Assembly: Numeric jump labels must be annotated with a suffix.
        # Jumping backward in code requires appending 'b' (e.g., "1b"), and
        # jumping forward requires appending 'f' (e.g., "1f").
        # Proper support for generating these labels is currently unimplemented.
        raise NotImplementedError(
            "Assembly printing for jumps to numeric labels not implemented"
        )
    return (then_label_str,)

print(printer: Printer) -> None

Source code in xdsl/dialects/x86/ops.py

def print(self, printer: Printer) -> None:
    printer.print_string(" ")
    print_type_pair(printer, self.rflags)
    printer.print_string(", ")
    printer.print_block_name(self.then_block)
    printer.print_string("(")
    printer.print_list(self.then_values, lambda val: print_type_pair(printer, val))
    printer.print_string("), ")
    printer.print_block_name(self.else_block)
    printer.print_string("(")
    printer.print_list(self.else_values, lambda val: print_type_pair(printer, val))
    printer.print_string(")")
    if self.attributes:
        printer.print_op_attributes(
            self.attributes,
            reserved_attr_names="operandSegmentSizes",
            print_keyword=True,
        )

parse(parser: Parser) -> Self classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse(cls, parser: Parser) -> Self:
    rflags = parse_type_pair(parser)
    parser.parse_punctuation(",")
    then_block = parser.parse_successor()
    then_args = parser.parse_comma_separated_list(
        parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
    )
    parser.parse_punctuation(",")
    else_block = parser.parse_successor()
    else_args = parser.parse_comma_separated_list(
        parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
    )
    attrs = parser.parse_optional_attr_dict_with_keyword()
    op = cls(rflags, then_args, else_args, then_block, else_block)
    if attrs is not None:
        op.attributes |= attrs.data
    return op

RSS_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]

A base class for x86 operations that have one register that is read and written to, and two source registers.

Source code in xdsl/dialects/x86/ops.py

class RSS_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]):
    """
    A base class for x86 operations that have one register that is read and written to,
    and two source registers.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)
    source1 = operand_def(R2InvT)
    source2 = operand_def(R3InvT)

    assembly_format = (
        "$register_in `,` $source1 `,` $source2 attr-dict `:` "
        "`(` type($register_in) `,` type($source1) `,` type($source2) `)` `->` type($register_out)"
    )

    def __init__(
        self,
        register_in: SSAValue[R1InvT],
        source1: Operation | SSAValue,
        source2: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        if register_out is None:
            register_out = register_in.type

        super().__init__(
            operands=[register_in, source1, source2],
            attributes={
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (
            reg(self.register_in),
            reg(self.source1),
            reg(self.source2),
        )

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.source1, self.source2), (), ((self.register_in, self.register_out),)
        )

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source1 = operand_def(R2InvT) class-attribute instance-attribute

source2 = operand_def(R3InvT) class-attribute instance-attribute

assembly_format = '$register_in `,` $source1 `,` $source2 attr-dict `:` `(` type($register_in) `,` type($source1) `,` type($source2) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: SSAValue[R1InvT], source1: Operation | SSAValue, source2: Operation | SSAValue, *, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: SSAValue[R1InvT],
    source1: Operation | SSAValue,
    source2: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    if register_out is None:
        register_out = register_in.type

    super().__init__(
        operands=[register_in, source1, source2],
        attributes={
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (
        reg(self.register_in),
        reg(self.source1),
        reg(self.source2),
    )

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.source1, self.source2), (), ((self.register_in, self.register_out),)
    )

RSSK_Operation

Bases: X86Instruction, ABC

A base class for x86 AVX512 operations that have one register r that is read and written to, and two source registers s1 and s2, with mask register k. The z attribute enables zero masking, which sets the elements of the destination register to zero where the corresponding bit in the mask is zero.

Source code in xdsl/dialects/x86/ops.py

class RSSK_Operation(X86Instruction, ABC):
    """
    A base class for x86 AVX512 operations that have one register r that is read and written to,
    and two source registers s1 and s2, with mask register k. The z attribute enables zero masking,
    which sets the elements of the destination register to zero where the corresponding
    bit in the mask is zero.
    """

    T: ClassVar[VarConstraint] = VarConstraint("T", base(X86VectorRegisterType))

    register_in = operand_def(T)
    register_out = result_def(T)
    source1 = operand_def(X86VectorRegisterType)
    source2 = operand_def(X86VectorRegisterType)
    mask_reg = operand_def(AVX512MaskRegisterType)
    z = opt_attr_def(UnitAttr)

    assembly_format = (
        "$register_in `,` $source1 `,` $source2 `,` $mask_reg attr-dict `:` "
        "`(` type($register_in) `,` type($source1) `,` type($source2) `,` type($mask_reg) `)` `->` type($register_out)"
    )

    def __init__(
        self,
        register_in: SSAValue[R1InvT],
        source1: Operation | SSAValue,
        source2: Operation | SSAValue,
        mask_reg: Operation | SSAValue,
        *,
        z: bool = False,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        if register_out is None:
            register_out = register_in.type

        super().__init__(
            operands=[register_in, source1, source2, mask_reg],
            attributes={
                "z": UnitAttr() if z else None,
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        register_in = masked_source_str(self.register_in, self.mask_reg, self.z)
        return register_in, reg(self.source1), reg(self.source2)

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.source1, self.source2, self.mask_reg),
            (),
            ((self.register_in, self.register_out),),
        )

T: VarConstraint = VarConstraint('T', base(X86VectorRegisterType)) class-attribute

register_in = operand_def(T) class-attribute instance-attribute

register_out = result_def(T) class-attribute instance-attribute

source1 = operand_def(X86VectorRegisterType) class-attribute instance-attribute

source2 = operand_def(X86VectorRegisterType) class-attribute instance-attribute

mask_reg = operand_def(AVX512MaskRegisterType) class-attribute instance-attribute

z = opt_attr_def(UnitAttr) class-attribute instance-attribute

assembly_format = '$register_in `,` $source1 `,` $source2 `,` $mask_reg attr-dict `:` `(` type($register_in) `,` type($source1) `,` type($source2) `,` type($mask_reg) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: SSAValue[R1InvT], source1: Operation | SSAValue, source2: Operation | SSAValue, mask_reg: Operation | SSAValue, *, z: bool = False, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: SSAValue[R1InvT],
    source1: Operation | SSAValue,
    source2: Operation | SSAValue,
    mask_reg: Operation | SSAValue,
    *,
    z: bool = False,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    if register_out is None:
        register_out = register_in.type

    super().__init__(
        operands=[register_in, source1, source2, mask_reg],
        attributes={
            "z": UnitAttr() if z else None,
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    register_in = masked_source_str(self.register_in, self.mask_reg, self.z)
    return register_in, reg(self.source1), reg(self.source2)

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.source1, self.source2, self.mask_reg),
        (),
        ((self.register_in, self.register_out),),
    )

DSS_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]

A base class for x86 operations that have one destination register and two source registers.

Source code in xdsl/dialects/x86/ops.py

class DSS_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]):
    """
    A base class for x86 operations that have one destination register and two source
    registers.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    source1 = operand_def(R2InvT)
    source2 = operand_def(R3InvT)

    assembly_format = (
        "$source1 `,` $source2 attr-dict `:` "
        "`(` type($source1) `,` type($source2) `)` `->` type($destination)"
    )

    def __init__(
        self,
        source1: Operation | SSAValue[R2InvT],
        source2: Operation | SSAValue[R3InvT],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source1, source2],
            attributes={
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.destination), reg(self.source1), reg(self.source2)

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.source1, self.source2), (self.destination,), ()
        )

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source1 = operand_def(R2InvT) class-attribute instance-attribute

source2 = operand_def(R3InvT) class-attribute instance-attribute

assembly_format = '$source1 `,` $source2 attr-dict `:` `(` type($source1) `,` type($source2) `)` `->` type($destination)' class-attribute instance-attribute

__init__(source1: Operation | SSAValue[R2InvT], source2: Operation | SSAValue[R3InvT], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source1: Operation | SSAValue[R2InvT],
    source2: Operation | SSAValue[R3InvT],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source1, source2],
        attributes={
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.destination), reg(self.source1), reg(self.source2)

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.source1, self.source2), (self.destination,), ()
    )

DSM_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]

A base class for x86 operations that have one destination register, one source register, and one memory source operand.

Source code in xdsl/dialects/x86/ops.py

class DSM_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]):
    """
    A base class for x86 operations that have one destination register, one source
    register, and one memory source operand.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    source = operand_def(R2InvT)
    memory = operand_def(R3InvT)
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "$source `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($source) `,` type($memory) `)` `->` type($destination)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[SI64],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source, memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return reg(self.destination), reg(self.source), memory_access

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source = operand_def(R2InvT) class-attribute instance-attribute

memory = operand_def(R3InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '$source `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($source) `,` type($memory) `)` `->` type($destination)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, memory: Operation | SSAValue, memory_offset: int | IntegerAttr[SI64], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[SI64],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source, memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return reg(self.destination), reg(self.source), memory_access

RSM_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT, R4InvT]

A base class for x86 operations that have one register that is read and written to, one source register and one memory source operand.

Source code in xdsl/dialects/x86/ops.py

class RSM_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT, R4InvT]):
    """
    A base class for x86 operations that have one register that is read and written to,
    one source register and one memory source operand.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)
    source1 = operand_def(R2InvT)
    memory = operand_def(R4InvT)
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "$register_in `,` $source1 `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($register_in) `,` type($source1) `,` type($memory) `)` "
        "`->` type($register_out)"
    )

    def __init__(
        self,
        register_in: SSAValue[R1InvT],
        source1: Operation | SSAValue,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[SI64],
        *,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        if register_out is None:
            register_out = register_in.type

        super().__init__(
            operands=[register_in, source1, memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[register_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        src1 = reg(self.source1)
        destination = reg(self.register_in)
        return destination, src1, memory_access

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.source1, self.memory), (), ((self.register_in, self.register_out),)
        )

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source1 = operand_def(R2InvT) class-attribute instance-attribute

memory = operand_def(R4InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '$register_in `,` $source1 `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($register_in) `,` type($source1) `,` type($memory) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: SSAValue[R1InvT], source1: Operation | SSAValue, memory: Operation | SSAValue, memory_offset: int | IntegerAttr[SI64], *, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: SSAValue[R1InvT],
    source1: Operation | SSAValue,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[SI64],
    *,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    if register_out is None:
        register_out = register_in.type

    super().__init__(
        operands=[register_in, source1, memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[register_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    src1 = reg(self.source1)
    destination = reg(self.register_in)
    return destination, src1, memory_access

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.source1, self.memory), (), ((self.register_in, self.register_out),)
    )

RSMB_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT, R4InvT]

A base class for x86 operations that have one register that is read and written to, one source register, and one memory source operand. When the broadcast attribute is set, the memory operand uses EVEX broadcast encoding.

Source code in xdsl/dialects/x86/ops.py

class RSMB_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT, R4InvT]):
    """
    A base class for x86 operations that have one register that is read and written to,
    one source register, and one memory source operand. When the broadcast attribute is
    set, the memory operand uses EVEX broadcast encoding.
    """

    register_in = operand_def(R1InvT)
    register_out: OpResult[R1InvT] = result_def(R1InvT)
    source1 = operand_def(R2InvT)
    memory = operand_def(R4InvT)
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))
    broadcast = opt_attr_def(UnitAttr)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "$register_in `,` $source1 `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($register_in) `,` type($source1) `,` type($memory) `)` "
        "`->` type($register_out)"
    )

    def __init__(
        self,
        register_in: SSAValue[R1InvT],
        source1: Operation | SSAValue,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[SI64],
        *,
        broadcast: bool = False,
        comment: str | StringAttr | None = None,
        register_out: R1InvT | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        if register_out is None:
            register_out = register_in.type

        super().__init__(
            operands=[register_in, source1, memory],
            attributes={
                "memory_offset": memory_offset,
                "broadcast": UnitAttr() if broadcast else None,
                "comment": comment,
            },
            result_types=[register_out],
        )

    @classmethod
    @abstractmethod
    def lane_bitwidth(cls) -> int:
        """
        The bitwidth of a single lane of the vector this operation operates on.
        """
        raise NotImplementedError()

    def broadcast_modifier(self) -> str:
        """
        The EVEX broadcast modifier for this operation, e.g. `1to8`.

        The lane count is the register width divided by the lane width, so it
        depends on the register bank this operation is allocated to: vfmadd231pd
        broadcasts `1to2` on xmm, `1to4` on ymm and `1to8` on zmm.
        """
        register_type = self.register_in.type
        assert isinstance(register_type, X86VectorRegisterType)
        return f"1to{register_type.bitwidth() // self.lane_bitwidth()}"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        if self.broadcast:
            memory_access = broadcast_memory_access_str(
                self.memory,
                self.memory_offset,
                self.broadcast_modifier(),
            )
        else:
            memory_access = memory_access_str(self.memory, self.memory_offset)
        return reg(self.register_in), reg(self.source1), memory_access

    def get_register_constraints(self) -> RegisterConstraints:
        return RegisterConstraints(
            (self.source1, self.memory), (), ((self.register_in, self.register_out),)
        )

register_in = operand_def(R1InvT) class-attribute instance-attribute

register_out: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source1 = operand_def(R2InvT) class-attribute instance-attribute

memory = operand_def(R4InvT) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

broadcast = opt_attr_def(UnitAttr) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '$register_in `,` $source1 `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($register_in) `,` type($source1) `,` type($memory) `)` `->` type($register_out)' class-attribute instance-attribute

__init__(register_in: SSAValue[R1InvT], source1: Operation | SSAValue, memory: Operation | SSAValue, memory_offset: int | IntegerAttr[SI64], *, broadcast: bool = False, comment: str | StringAttr | None = None, register_out: R1InvT | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_in: SSAValue[R1InvT],
    source1: Operation | SSAValue,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[SI64],
    *,
    broadcast: bool = False,
    comment: str | StringAttr | None = None,
    register_out: R1InvT | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    if register_out is None:
        register_out = register_in.type

    super().__init__(
        operands=[register_in, source1, memory],
        attributes={
            "memory_offset": memory_offset,
            "broadcast": UnitAttr() if broadcast else None,
            "comment": comment,
        },
        result_types=[register_out],
    )

lane_bitwidth() -> int abstractmethod classmethod

The bitwidth of a single lane of the vector this operation operates on.

Source code in xdsl/dialects/x86/ops.py

@classmethod
@abstractmethod
def lane_bitwidth(cls) -> int:
    """
    The bitwidth of a single lane of the vector this operation operates on.
    """
    raise NotImplementedError()

broadcast_modifier() -> str

The EVEX broadcast modifier for this operation, e.g. 1to8.

The lane count is the register width divided by the lane width, so it depends on the register bank this operation is allocated to: vfmadd231pd broadcasts 1to2 on xmm, 1to4 on ymm and 1to8 on zmm.

Source code in xdsl/dialects/x86/ops.py

def broadcast_modifier(self) -> str:
    """
    The EVEX broadcast modifier for this operation, e.g. `1to8`.

    The lane count is the register width divided by the lane width, so it
    depends on the register bank this operation is allocated to: vfmadd231pd
    broadcasts `1to2` on xmm, `1to4` on ymm and `1to8` on zmm.
    """
    register_type = self.register_in.type
    assert isinstance(register_type, X86VectorRegisterType)
    return f"1to{register_type.bitwidth() // self.lane_bitwidth()}"

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    if self.broadcast:
        memory_access = broadcast_memory_access_str(
            self.memory,
            self.memory_offset,
            self.broadcast_modifier(),
        )
    else:
        memory_access = memory_access_str(self.memory, self.memory_offset)
    return reg(self.register_in), reg(self.source1), memory_access

get_register_constraints() -> RegisterConstraints

Source code in xdsl/dialects/x86/ops.py

def get_register_constraints(self) -> RegisterConstraints:
    return RegisterConstraints(
        (self.source1, self.memory), (), ((self.register_in, self.register_out),)
    )

DSSI_Operation

Bases: X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]

A base class for x86 operations that have one destination register, one source register and an immediate value.

Source code in xdsl/dialects/x86/ops.py

class DSSI_Operation(X86Instruction, ABC, Generic[R1InvT, R2InvT, R3InvT]):
    """
    A base class for x86 operations that have one destination register, one source
    register and an immediate value.
    """

    destination: OpResult[R1InvT] = result_def(R1InvT)
    source0 = operand_def(R2InvT)
    source1 = operand_def(R3InvT)
    immediate = attr_def(IntegerAttr[UI8])

    assembly_format = (
        "$source0 `,` $source1 `,` $immediate attr-dict "
        "`:` `(` type($source0) `,` type($source1) `)` `->`  type($destination)"
    )

    def __init__(
        self,
        source0: Operation | SSAValue,
        source1: Operation | SSAValue,
        immediate: int | IntegerAttr[UI8],
        *,
        comment: str | StringAttr | None = None,
        destination: R1InvT,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, ui8)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source0, source1],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
            result_types=[destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (
            reg(self.destination),
            reg(self.source0),
            reg(self.source1),
            self.immediate,
        )

destination: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

source0 = operand_def(R2InvT) class-attribute instance-attribute

source1 = operand_def(R3InvT) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[UI8]) class-attribute instance-attribute

assembly_format = '$source0 `,` $source1 `,` $immediate attr-dict `:` `(` type($source0) `,` type($source1) `)` `->` type($destination)' class-attribute instance-attribute

__init__(source0: Operation | SSAValue, source1: Operation | SSAValue, immediate: int | IntegerAttr[UI8], *, comment: str | StringAttr | None = None, destination: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source0: Operation | SSAValue,
    source1: Operation | SSAValue,
    immediate: int | IntegerAttr[UI8],
    *,
    comment: str | StringAttr | None = None,
    destination: R1InvT,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, ui8)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source0, source1],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
        result_types=[destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (
        reg(self.destination),
        reg(self.source0),
        reg(self.source1),
        self.immediate,
    )

RS_AddOpHasCanonicalizationPatterns dataclass

Bases: HasCanonicalizationPatternsTrait

Source code in xdsl/dialects/x86/ops.py

class RS_AddOpHasCanonicalizationPatterns(HasCanonicalizationPatternsTrait):
    @classmethod
    def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
        from xdsl.transforms.canonicalization_patterns.x86 import RS_Add_Zero

        return (RS_Add_Zero(),)

get_canonicalization_patterns() -> tuple[RewritePattern, ...] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
    from xdsl.transforms.canonicalization_patterns.x86 import RS_Add_Zero

    return (RS_Add_Zero(),)

RS_AddOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

Adds the registers r and s and stores the result in r.

x[r] = x[r] + x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_AddOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Adds the registers r and s and stores the result in r.
    ```C
    x[r] = x[r] + x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/add).
    """

    name = "x86.rs.add"

    traits = traits_def(AlwaysSpeculatable(), RS_AddOpHasCanonicalizationPatterns())

name = 'x86.rs.add' class-attribute instance-attribute

traits = traits_def(AlwaysSpeculatable(), RS_AddOpHasCanonicalizationPatterns()) class-attribute instance-attribute

RS_SubOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

subtracts s from r and stores the result in r.

x[r] = x[r] - x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_SubOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    subtracts s from r and stores the result in r.
    ```C
    x[r] = x[r] - x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/sub).
    """

    name = "x86.rs.sub"

name = 'x86.rs.sub' class-attribute instance-attribute

RS_ImulOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

Multiplies the registers r and s and stores the result in r.

x[r] = x[r] * x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_ImulOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Multiplies the registers r and s and stores the result in r.
    ```C
    x[r] = x[r] * x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/imul).
    """

    name = "x86.rs.imul"

name = 'x86.rs.imul' class-attribute instance-attribute

RS_FAddOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

Adds the floating point values in registers r and s and stores the result in r.

x[r] += x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_FAddOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Adds the floating point values in registers r and s and stores the result in r.
    ```C
    x[r] += x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/fadd:faddp:fiadd).
    """

    name = "x86.rs.fadd"

name = 'x86.rs.fadd' class-attribute instance-attribute

RS_FMulOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

Multiplies the floating point values in registers r and s and stores the result in r.

x[r] *= x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_FMulOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Multiplies the floating point values in registers r and s and stores the result in
    r.
    ```C
    x[r] *= x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/fmul:fmulp:fimul).
    """

    name = "x86.rs.fmul"

name = 'x86.rs.fmul' class-attribute instance-attribute

RS_AndOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise and of r and s, stored in r

x[r] = x[r] & x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_AndOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise and of r and s, stored in r
    ```C
    x[r] = x[r] & x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/and).
    """

    name = "x86.rs.and"

name = 'x86.rs.and' class-attribute instance-attribute

RS_OrOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise or of r and s, stored in r

x[r] = x[r] | x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_OrOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise or of r and s, stored in r
    ```C
    x[r] = x[r] | x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/or).
    """

    name = "x86.rs.or"

name = 'x86.rs.or' class-attribute instance-attribute

RS_XorOp dataclass

Bases: RS_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise xor of r and s, stored in r

x[r] = x[r] ^ x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RS_XorOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise xor of r and s, stored in r
    ```C
    x[r] = x[r] ^ x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/xor).
    """

    name = "x86.rs.xor"

name = 'x86.rs.xor' class-attribute instance-attribute

DS_MovOpHasCanonicalizationPatterns dataclass

Bases: HasCanonicalizationPatternsTrait

Source code in xdsl/dialects/x86/ops.py

class DS_MovOpHasCanonicalizationPatterns(HasCanonicalizationPatternsTrait):
    @classmethod
    def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
        from xdsl.transforms.canonicalization_patterns.x86 import RemoveRedundantDS_Mov

        return (RemoveRedundantDS_Mov(),)

get_canonicalization_patterns() -> tuple[RewritePattern, ...] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
    from xdsl.transforms.canonicalization_patterns.x86 import RemoveRedundantDS_Mov

    return (RemoveRedundantDS_Mov(),)

DS_MovOp dataclass

Bases: DS_Operation[GeneralRegisterType, GeneralRegisterType]

Copies the value of s into r.

x[r] = x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DS_MovOp(DS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Copies the value of s into r.
    ```C
    x[r] = x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/mov).
    """

    name = "x86.ds.mov"

    traits = traits_def(AlwaysSpeculatable(), DS_MovOpHasCanonicalizationPatterns())

name = 'x86.ds.mov' class-attribute instance-attribute

traits = traits_def(AlwaysSpeculatable(), DS_MovOpHasCanonicalizationPatterns()) class-attribute instance-attribute

DS_VpbroadcastdOp dataclass

Bases: DS_Operation[X86VectorRegisterType, GeneralRegisterType]

Broadcast single precision floating-point scalar in s to d.

x[r] = x[s]

See external documentation

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DS_VpbroadcastdOp(DS_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Broadcast single precision floating-point scalar in s to d.
    ```C
    x[r] = x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/vpbroadcast)
    """

    name = "x86.ds.vpbroadcastd"

name = 'x86.ds.vpbroadcastd' class-attribute instance-attribute

DS_VpbroadcastqOp dataclass

Bases: DS_Operation[X86VectorRegisterType, GeneralRegisterType]

Broadcast double precision floating-point scalar in s to d.

x[r] = x[s]

See external documentation

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DS_VpbroadcastqOp(DS_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Broadcast double precision floating-point scalar in s to d.
    ```C
    x[r] = x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/vpbroadcast)
    """

    name = "x86.ds.vpbroadcastq"

name = 'x86.ds.vpbroadcastq' class-attribute instance-attribute

S_PushOp

Bases: X86Instruction

Decreases %rsp and places s at the new memory location pointed to by %rsp.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class S_PushOp(X86Instruction):
    """
    Decreases %rsp and places s at the new memory location pointed to by %rsp.

    See external [documentation](https://www.felixcloutier.com/x86/push).
    """

    name = "x86.s.push"

    rsp_in = operand_def(RSP)
    rsp_out = result_def(RSP)
    source = operand_def(GeneralRegisterType)

    assembly_format = (
        "$rsp_in `,` $source attr-dict `:` "
        "`(` type($rsp_in) `,` type($source) `)` `->` type($rsp_out)"
    )

    def __init__(
        self,
        rsp_in: Operation | SSAValue,
        source: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rsp_in, source],
            attributes={
                "comment": comment,
            },
            result_types=[RSP],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (reg(self.source),)

name = 'x86.s.push' class-attribute instance-attribute

rsp_in = operand_def(RSP) class-attribute instance-attribute

rsp_out = result_def(RSP) class-attribute instance-attribute

source = operand_def(GeneralRegisterType) class-attribute instance-attribute

assembly_format = '$rsp_in `,` $source attr-dict `:` `(` type($rsp_in) `,` type($source) `)` `->` type($rsp_out)' class-attribute instance-attribute

__init__(rsp_in: Operation | SSAValue, source: Operation | SSAValue, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    rsp_in: Operation | SSAValue,
    source: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rsp_in, source],
        attributes={
            "comment": comment,
        },
        result_types=[RSP],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (reg(self.source),)

D_PopOp

Bases: X86Instruction

Copies the value at the top of the stack into d and increases %rsp.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class D_PopOp(X86Instruction):
    """
    Copies the value at the top of the stack into d and increases %rsp.

    See external [documentation](https://www.felixcloutier.com/x86/pop).
    """

    name = "x86.d.pop"

    rsp_in = operand_def(RSP)
    rsp_out = result_def(RSP)
    destination: OpResult[GeneralRegisterType] = result_def(GeneralRegisterType)

    assembly_format = (
        "$rsp_in attr-dict `:` "
        "`(` type($rsp_in) `)` `->` `(` type($rsp_out) `,` type($destination) `)`"
    )

    def __init__(
        self,
        rsp_in: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        destination: X86RegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rsp_in],
            attributes={
                "comment": comment,
            },
            result_types=[RSP, destination],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (reg(self.destination),)

name = 'x86.d.pop' class-attribute instance-attribute

rsp_in = operand_def(RSP) class-attribute instance-attribute

rsp_out = result_def(RSP) class-attribute instance-attribute

destination: OpResult[GeneralRegisterType] = result_def(GeneralRegisterType) class-attribute instance-attribute

assembly_format = '$rsp_in attr-dict `:` `(` type($rsp_in) `)` `->` `(` type($rsp_out) `,` type($destination) `)`' class-attribute instance-attribute

__init__(rsp_in: Operation | SSAValue, *, comment: str | StringAttr | None = None, destination: X86RegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    rsp_in: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    destination: X86RegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rsp_in],
        attributes={
            "comment": comment,
        },
        result_types=[RSP, destination],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (reg(self.destination),)

R_NegOp dataclass

Bases: R_Operation[GeneralRegisterType]

Negates r and stores the result in r.

x[r] = -x[r]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class R_NegOp(R_Operation[GeneralRegisterType]):
    """
    Negates r and stores the result in r.
    ```C
    x[r] = -x[r]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/neg).
    """

    name = "x86.r.neg"

name = 'x86.r.neg' class-attribute instance-attribute

R_NotOp dataclass

Bases: R_Operation[GeneralRegisterType]

bitwise not of r, stored in r

x[r] = ~x[r]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class R_NotOp(R_Operation[GeneralRegisterType]):
    """
    bitwise not of r, stored in r
    ```C
    x[r] = ~x[r]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/not).
    """

    name = "x86.r.not"

name = 'x86.r.not' class-attribute instance-attribute

R_IncOp dataclass

Bases: R_Operation[GeneralRegisterType]

Increments r by 1 and stores the result in r.

x[r] = x[r] + 1

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class R_IncOp(R_Operation[GeneralRegisterType]):
    """
    Increments r by 1 and stores the result in r.
    ```C
    x[r] = x[r] + 1
    ```

    See external [documentation](https://www.felixcloutier.com/x86/inc).
    """

    name = "x86.r.inc"

name = 'x86.r.inc' class-attribute instance-attribute

R_DecOp dataclass

Bases: R_Operation[GeneralRegisterType]

Decrements r by 1 and stores the result in r.

x[r] = x[r] - 1

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class R_DecOp(R_Operation[GeneralRegisterType]):
    """
    Decrements r by 1 and stores the result in r.
    ```C
    x[r] = x[r] - 1
    ```

    See external [documentation](https://www.felixcloutier.com/x86/dec).
    """

    name = "x86.r.dec"

name = 'x86.r.dec' class-attribute instance-attribute

S_IDivOp

Bases: X86Instruction

Divides the value in RDX:RAX by s and stores the quotient in RAX and the remainder in RDX.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class S_IDivOp(X86Instruction):
    """
    Divides the value in RDX:RAX by s and stores the quotient in RAX and the remainder
    in RDX.

    See external [documentation](https://www.felixcloutier.com/x86/idiv).
    """

    name = "x86.s.idiv"

    source = operand_def(X86RegisterType)
    rdx_input = operand_def(RDX)
    rax_input = operand_def(RAX)

    rdx_output = result_def(RDX)
    rax_output = result_def(RAX)

    assembly_format = (
        "$source `,` $rdx_input `,` $rax_input attr-dict `:` "
        "`(` type($source) `,` type($rdx_input) `,` type($rax_input) `)` "
        "`->` `(` type($rdx_output) `,` type($rax_output) `)`"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        rdx_input: Operation | SSAValue,
        rax_input: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        rdx_output: GeneralRegisterType,
        rax_output: GeneralRegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source, rdx_input, rax_input],
            attributes={
                "comment": comment,
            },
            result_types=[rdx_output, rax_output],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (reg(self.source),)

name = 'x86.s.idiv' class-attribute instance-attribute

source = operand_def(X86RegisterType) class-attribute instance-attribute

rdx_input = operand_def(RDX) class-attribute instance-attribute

rax_input = operand_def(RAX) class-attribute instance-attribute

rdx_output = result_def(RDX) class-attribute instance-attribute

rax_output = result_def(RAX) class-attribute instance-attribute

assembly_format = '$source `,` $rdx_input `,` $rax_input attr-dict `:` `(` type($source) `,` type($rdx_input) `,` type($rax_input) `)` `->` `(` type($rdx_output) `,` type($rax_output) `)`' class-attribute instance-attribute

__init__(source: Operation | SSAValue, rdx_input: Operation | SSAValue, rax_input: Operation | SSAValue, *, comment: str | StringAttr | None = None, rdx_output: GeneralRegisterType, rax_output: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    rdx_input: Operation | SSAValue,
    rax_input: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    rdx_output: GeneralRegisterType,
    rax_output: GeneralRegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source, rdx_input, rax_input],
        attributes={
            "comment": comment,
        },
        result_types=[rdx_output, rax_output],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (reg(self.source),)

S_ImulOp

Bases: X86Instruction

The source operand is multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.

x[RDX:RAX] = x[RAX] * s

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class S_ImulOp(X86Instruction):
    """
    The source operand is multiplied by the value in the RAX register and the product is
    stored in the RDX:RAX registers.
    ```C
    x[RDX:RAX] = x[RAX] * s
    ```

    See external [documentation](https://www.felixcloutier.com/x86/imul).
    """

    name = "x86.s.imul"

    source = operand_def(GeneralRegisterType)
    rax_input = operand_def(RAX)

    rdx_output = result_def(RDX)
    rax_output = result_def(RAX)

    assembly_format = (
        "$source `,` $rax_input attr-dict `:` "
        "`(` type($source) `,` type($rax_input) `)` "
        "`->` `(` type($rdx_output) `,` type($rax_output) `)`"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        rax_input: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        rdx_output: GeneralRegisterType,
        rax_output: GeneralRegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source, rax_input],
            attributes={
                "comment": comment,
            },
            result_types=[rdx_output, rax_output],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return (reg(self.source),)

name = 'x86.s.imul' class-attribute instance-attribute

source = operand_def(GeneralRegisterType) class-attribute instance-attribute

rax_input = operand_def(RAX) class-attribute instance-attribute

rdx_output = result_def(RDX) class-attribute instance-attribute

rax_output = result_def(RAX) class-attribute instance-attribute

assembly_format = '$source `,` $rax_input attr-dict `:` `(` type($source) `,` type($rax_input) `)` `->` `(` type($rdx_output) `,` type($rax_output) `)`' class-attribute instance-attribute

__init__(source: Operation | SSAValue, rax_input: Operation | SSAValue, *, comment: str | StringAttr | None = None, rdx_output: GeneralRegisterType, rax_output: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    rax_input: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    rdx_output: GeneralRegisterType,
    rax_output: GeneralRegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source, rax_input],
        attributes={
            "comment": comment,
        },
        result_types=[rdx_output, rax_output],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return (reg(self.source),)

RM_AddOp dataclass

Bases: RM_Operation[GeneralRegisterType, GeneralRegisterType]

Adds the value from the memory location pointed to by m to r and stores the result in r.

x[r] = x[r] + [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RM_AddOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Adds the value from the memory location pointed to by m to r and stores the result
    in r.
    ```C
    x[r] = x[r] + [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/add).
    """

    name = "x86.rm.add"

name = 'x86.rm.add' class-attribute instance-attribute

RM_SubOp dataclass

Bases: RM_Operation[GeneralRegisterType, GeneralRegisterType]

Subtracts the value from the memory location pointed to by m from r and stores the result in r.

x[r] = x[r] - [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RM_SubOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Subtracts the value from the memory location pointed to by m from r and stores the
    result in r.
    ```C
    x[r] = x[r] - [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/sub).
    """

    name = "x86.rm.sub"

name = 'x86.rm.sub' class-attribute instance-attribute

RM_ImulOp dataclass

Bases: RM_Operation[GeneralRegisterType, GeneralRegisterType]

Multiplies the value from the memory location pointed to by m with r and stores the result in r.

x[r] = x[r] * [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RM_ImulOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Multiplies the value from the memory location pointed to by m with r and stores the
    result in r.
    ```C
    x[r] = x[r] * [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/imul).
    """

    name = "x86.rm.imul"

name = 'x86.rm.imul' class-attribute instance-attribute

RM_AndOp dataclass

Bases: RM_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise and of r and [m], stored in r

x[r] = x[r] & [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RM_AndOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise and of r and [m], stored in r
    ```C
    x[r] = x[r] & [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/and).
    """

    name = "x86.rm.and"

name = 'x86.rm.and' class-attribute instance-attribute

RM_OrOp dataclass

Bases: RM_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise or of r and [m], stored in r

x[r] = x[r] | [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RM_OrOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise or of r and [m], stored in r
    ```C
    x[r] = x[r] | [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/or).
    """

    name = "x86.rm.or"

name = 'x86.rm.or' class-attribute instance-attribute

RM_XorOp dataclass

Bases: RM_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise xor of r and [m], stored in r

x[r] = x[r] ^ [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RM_XorOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise xor of r and [m], stored in r
    ```C
    x[r] = x[r] ^ [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/xor).
    """

    name = "x86.rm.xor"

name = 'x86.rm.xor' class-attribute instance-attribute

DM_MovOp dataclass

Bases: DM_Operation[GeneralRegisterType, GeneralRegisterType]

Copies the value from the memory location pointed to by source register m into destination register d.

x[d] = [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_MovOp(DM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Copies the value from the memory location pointed to by source register m into destination register d.
    ```C
    x[d] = [x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/mov).
    """

    name = "x86.dm.mov"

name = 'x86.dm.mov' class-attribute instance-attribute

DM_LeaOp dataclass

Bases: DM_Operation[GeneralRegisterType, GeneralRegisterType]

Loads the effective address of the memory location pointed to by m into d.

x[d] = &x[m]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_LeaOp(DM_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Loads the effective address of the memory location pointed to by m into d.
    ```C
    x[d] = &x[m]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/lea).
    """

    name = "x86.dm.lea"

name = 'x86.dm.lea' class-attribute instance-attribute

RI_AddOp dataclass

Bases: RI_Operation[GeneralRegisterType]

Adds the immediate value to r and stores the result in r.

x[r] = x[r] + immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RI_AddOp(RI_Operation[GeneralRegisterType]):
    """
    Adds the immediate value to r and stores the result in r.
    ```C
    x[r] = x[r] + immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/add).
    """

    name = "x86.ri.add"

name = 'x86.ri.add' class-attribute instance-attribute

RI_SubOp dataclass

Bases: RI_Operation[GeneralRegisterType]

Subtracts the immediate value from r and stores the result in r.

x[r] = x[r] - immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RI_SubOp(RI_Operation[GeneralRegisterType]):
    """
    Subtracts the immediate value from r and stores the result in r.
    ```C
    x[r] = x[r] - immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/sub).
    """

    name = "x86.ri.sub"

name = 'x86.ri.sub' class-attribute instance-attribute

RI_AndOp dataclass

Bases: RI_Operation[GeneralRegisterType]

bitwise and of r and immediate, stored in r

x[r] = x[r] & immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RI_AndOp(RI_Operation[GeneralRegisterType]):
    """
    bitwise and of r and immediate, stored in r
    ```C
    x[r] = x[r] & immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/and).
    """

    name = "x86.ri.and"

name = 'x86.ri.and' class-attribute instance-attribute

RI_OrOp dataclass

Bases: RI_Operation[GeneralRegisterType]

bitwise or of r and immediate, stored in r

x[r] = x[r] | immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RI_OrOp(RI_Operation[GeneralRegisterType]):
    """
    bitwise or of r and immediate, stored in r
    ```C
    x[r] = x[r] | immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/or).
    """

    name = "x86.ri.or"

name = 'x86.ri.or' class-attribute instance-attribute

RI_XorOp dataclass

Bases: RI_Operation[GeneralRegisterType]

bitwise xor of r and immediate, stored in r

x[r] = x[r] ^ immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RI_XorOp(RI_Operation[GeneralRegisterType]):
    """
    bitwise xor of r and immediate, stored in r
    ```C
    x[r] = x[r] ^ immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/xor).
    """

    name = "x86.ri.xor"

name = 'x86.ri.xor' class-attribute instance-attribute

DI_MovOp dataclass

Bases: DI_Operation[GeneralRegisterType]

Copies the immediate value into r.

x[r] = immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DI_MovOp(DI_Operation[GeneralRegisterType]):
    """
    Copies the immediate value into r.
    ```C
    x[r] = immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/mov).
    """

    name = "x86.di.mov"

    traits = traits_def(AlwaysSpeculatable())

name = 'x86.di.mov' class-attribute instance-attribute

traits = traits_def(AlwaysSpeculatable()) class-attribute instance-attribute

MS_AddOp dataclass

Bases: MS_Operation[GeneralRegisterType, GeneralRegisterType]

Adds the value from s to the memory location pointed to by m.

[x[m]] = [x[m]] + x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_AddOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Adds the value from s to the memory location pointed to by m.
    ```C
    [x[m]] = [x[m]] + x[s]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/add).
    """

    name = "x86.ms.add"

    traits = traits_def(MemoryReadEffect())

name = 'x86.ms.add' class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

MS_SubOp dataclass

Bases: MS_Operation[GeneralRegisterType, GeneralRegisterType]

Subtracts the value from s from the memory location pointed to by m. [x[m]] = [x[m]] - x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_SubOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Subtracts the value from s from the memory location pointed to by m.
    [x[m]] = [x[m]] - x[s]

    See external [documentation](https://www.felixcloutier.com/x86/sub).
    """

    name = "x86.ms.sub"

    traits = traits_def(MemoryReadEffect())

name = 'x86.ms.sub' class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

MS_AndOp dataclass

Bases: MS_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise and of [m] and s [x[m]] = [x[m]] & x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_AndOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise and of [m] and s
    [x[m]] = [x[m]] & x[s]

    See external [documentation](https://www.felixcloutier.com/x86/and).
    """

    name = "x86.ms.and"

    traits = traits_def(MemoryReadEffect())

name = 'x86.ms.and' class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

MS_OrOp dataclass

Bases: MS_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise or of [m] and s [x[m]] = [x[m]] | x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_OrOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise or of [m] and s
    [x[m]] = [x[m]] | x[s]

    See external [documentation](https://www.felixcloutier.com/x86/or).
    """

    name = "x86.ms.or"

    traits = traits_def(MemoryReadEffect())

name = 'x86.ms.or' class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

MS_XorOp dataclass

Bases: MS_Operation[GeneralRegisterType, GeneralRegisterType]

bitwise xor of [m] and s [x[m]] = [x[m]] ^ x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_XorOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    bitwise xor of [m] and s
    [x[m]] = [x[m]] ^ x[s]

    See external [documentation](https://www.felixcloutier.com/x86/xor).
    """

    name = "x86.ms.xor"

    traits = traits_def(MemoryReadEffect())

name = 'x86.ms.xor' class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

MS_MovOp dataclass

Bases: MS_Operation[GeneralRegisterType, GeneralRegisterType]

Copies the value from s into the memory location pointed to by m. [x[m]] = x[s]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_MovOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Copies the value from s into the memory location pointed to by m.
    [x[m]] = x[s]

    See external [documentation](https://www.felixcloutier.com/x86/mov).
    """

    name = "x86.ms.mov"

name = 'x86.ms.mov' class-attribute instance-attribute

MI_AddOp dataclass

Bases: MI_Operation[GeneralRegisterType]

Adds the immediate value to the memory location pointed to by m. [x[m]] = [x[m]] + immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_AddOp(MI_Operation[GeneralRegisterType]):
    """
    Adds the immediate value to the memory location pointed to by m.
    [x[m]] = [x[m]] + immediate

    See external [documentation](https://www.felixcloutier.com/x86/add).
    """

    name = "x86.mi.add"

name = 'x86.mi.add' class-attribute instance-attribute

MI_SubOp dataclass

Bases: MI_Operation[GeneralRegisterType]

Subtracts the immediate value from the memory location pointed to by m. [x[m]] = [x[m]] - immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_SubOp(MI_Operation[GeneralRegisterType]):
    """
    Subtracts the immediate value from the memory location pointed to by m.
    [x[m]] = [x[m]] - immediate

    See external [documentation](https://www.felixcloutier.com/x86/sub).
    """

    name = "x86.mi.sub"

name = 'x86.mi.sub' class-attribute instance-attribute

MI_AndOp dataclass

Bases: MI_Operation[GeneralRegisterType]

bitwise and of immediate and [m], stored in [m]

[x[m]] = [x[m]] & immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_AndOp(MI_Operation[GeneralRegisterType]):
    """
    bitwise and of immediate and [m], stored in [m]
    ```C
    [x[m]] = [x[m]] & immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/and).
    """

    name = "x86.mi.and"

name = 'x86.mi.and' class-attribute instance-attribute

MI_OrOp dataclass

Bases: MI_Operation[GeneralRegisterType]

bitwise or of immediate and [m], stored in [m]

[x[m]] = [x[m]] | immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_OrOp(MI_Operation[GeneralRegisterType]):
    """
    bitwise or of immediate and [m], stored in [m]
    ```C
    [x[m]] = [x[m]] | immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/or).
    """

    name = "x86.mi.or"

name = 'x86.mi.or' class-attribute instance-attribute

MI_XorOp dataclass

Bases: MI_Operation[GeneralRegisterType]

bitwise xor of immediate and [m], stored in [m]

[x[m]] = [x[m]] ^ immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_XorOp(MI_Operation[GeneralRegisterType]):
    """
    bitwise xor of immediate and [m], stored in [m]
    ```C
    [x[m]] = [x[m]] ^ immediate
    ```

    See external [documentation](https://www.felixcloutier.com/x86/xor).
    """

    name = "x86.mi.xor"

name = 'x86.mi.xor' class-attribute instance-attribute

MI_MovOp dataclass

Bases: MI_Operation[GeneralRegisterType]

Copies the immediate value into the memory location pointed to by m. [x[m]] = immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_MovOp(MI_Operation[GeneralRegisterType]):
    """
    Copies the immediate value into the memory location pointed to by m.
    [x[m]] = immediate

    See external [documentation](https://www.felixcloutier.com/x86/mov).
    """

    name = "x86.mi.mov"

name = 'x86.mi.mov' class-attribute instance-attribute

DSI_ImulOp dataclass

Bases: DSI_Operation[GeneralRegisterType, GeneralRegisterType]

Multiplies the immediate value with the source register and stores the result in the destination register. x[d] = x[s] * immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSI_ImulOp(DSI_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Multiplies the immediate value with the source register and stores the result in the destination register.
    x[d] = x[s] * immediate

    See external [documentation](https://www.felixcloutier.com/x86/imul).
    """

    name = "x86.dsi.imul"

name = 'x86.dsi.imul' class-attribute instance-attribute

DMI_ImulOp dataclass

Bases: DMI_Operation[GeneralRegisterType, GeneralRegisterType]

Multiplies the immediate value with the memory location pointed to by m and stores the result in d. x[d] = [x[m]] * immediate

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DMI_ImulOp(DMI_Operation[GeneralRegisterType, GeneralRegisterType]):
    """
    Multiplies the immediate value with the memory location pointed to by m and stores the result in d.
    x[d] = [x[m]] * immediate

    See external [documentation](https://www.felixcloutier.com/x86/imul).
    """

    name = "x86.dmi.imul"

name = 'x86.dmi.imul' class-attribute instance-attribute

M_PushOp

Bases: X86Instruction

Decreases %rsp and places [m] at the new memory location pointed to by %rsp.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_PushOp(X86Instruction):
    """
    Decreases %rsp and places [m] at the new memory location pointed to by %rsp.

    See external [documentation](https://www.felixcloutier.com/x86/push).
    """

    name = "x86.m.push"

    rsp_in = operand_def(RSP)
    rsp_out = result_def(RSP)

    memory = operand_def(X86RegisterType)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))

    traits = traits_def(MemoryWriteEffect())

    assembly_format = (
        "$rsp_in `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($rsp_in) `,` type($memory) `)` `->` type($rsp_out)"
    )

    def __init__(
        self,
        rsp_in: Operation | SSAValue,
        memory: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        memory_offset: int | IntegerAttr,
        rsp_out: GeneralRegisterType,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)

        super().__init__(
            operands=[rsp_in, memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[rsp_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return (memory_access,)

name = 'x86.m.push' class-attribute instance-attribute

rsp_in = operand_def(RSP) class-attribute instance-attribute

rsp_out = result_def(RSP) class-attribute instance-attribute

memory = operand_def(X86RegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

traits = traits_def(MemoryWriteEffect()) class-attribute instance-attribute

assembly_format = '$rsp_in `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($rsp_in) `,` type($memory) `)` `->` type($rsp_out)' class-attribute instance-attribute

__init__(rsp_in: Operation | SSAValue, memory: Operation | SSAValue, *, comment: str | StringAttr | None = None, memory_offset: int | IntegerAttr, rsp_out: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    rsp_in: Operation | SSAValue,
    memory: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    memory_offset: int | IntegerAttr,
    rsp_out: GeneralRegisterType,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)

    super().__init__(
        operands=[rsp_in, memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[rsp_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return (memory_access,)

M_PopOp

Bases: X86Instruction

Copies the value at the top of the stack into [m] and increases %rsp. The value held by m is a pointer to the memory location where the value is stored. The only register modified by this operation is %rsp.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_PopOp(X86Instruction):
    """
    Copies the value at the top of the stack into [m] and increases %rsp.
    The value held by m is a pointer to the memory location where the value is stored.
    The only register modified by this operation is %rsp.

    See external [documentation](https://www.felixcloutier.com/x86/pop).
    """

    name = "x86.m.pop"

    rsp_in = operand_def(RSP)
    memory = operand_def(GeneralRegisterType)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))
    rsp_out = result_def(RSP)

    traits = traits_def(MemoryWriteEffect())

    assembly_format = (
        "$rsp_in `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($rsp_in) `,` type($memory) `)` `->` type($rsp_out)"
    )

    def __init__(
        self,
        rsp_in: Operation | SSAValue,
        memory: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
        memory_offset: int | IntegerAttr,
        rsp_out: GeneralRegisterType,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[rsp_in, memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[rsp_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return (memory_access,)

name = 'x86.m.pop' class-attribute instance-attribute

rsp_in = operand_def(RSP) class-attribute instance-attribute

memory = operand_def(GeneralRegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

rsp_out = result_def(RSP) class-attribute instance-attribute

traits = traits_def(MemoryWriteEffect()) class-attribute instance-attribute

assembly_format = '$rsp_in `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($rsp_in) `,` type($memory) `)` `->` type($rsp_out)' class-attribute instance-attribute

__init__(rsp_in: Operation | SSAValue, memory: Operation | SSAValue, *, comment: str | StringAttr | None = None, memory_offset: int | IntegerAttr, rsp_out: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    rsp_in: Operation | SSAValue,
    memory: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
    memory_offset: int | IntegerAttr,
    rsp_out: GeneralRegisterType,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[rsp_in, memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[rsp_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return (memory_access,)

M_NegOp dataclass

Bases: M_Operation[GeneralRegisterType]

Negates the value at the memory location pointed to by m.

[x[m]] = -[x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_NegOp(M_Operation[GeneralRegisterType]):
    """
    Negates the value at the memory location pointed to by m.
    ```C
    [x[m]] = -[x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/neg).
    """

    name = "x86.m.neg"

name = 'x86.m.neg' class-attribute instance-attribute

M_NotOp dataclass

Bases: M_Operation[GeneralRegisterType]

bitwise not of [m], stored in [m]

[x[m]] = ~[x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_NotOp(M_Operation[GeneralRegisterType]):
    """
    bitwise not of [m], stored in [m]
    ```C
    [x[m]] = ~[x[m]]
    ```

    See external [documentation](https://www.felixcloutier.com/x86/not).
    """

    name = "x86.m.not"

name = 'x86.m.not' class-attribute instance-attribute

M_IncOp dataclass

Bases: M_Operation[GeneralRegisterType]

Increments the value at the memory location pointed to by m. [x[m]] = [x[m]] + 1

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_IncOp(M_Operation[GeneralRegisterType]):
    """
    Increments the value at the memory location pointed to by m.
    [x[m]] = [x[m]] + 1

    See external [documentation](https://www.felixcloutier.com/x86/inc).
    """

    name = "x86.m.inc"

name = 'x86.m.inc' class-attribute instance-attribute

M_DecOp dataclass

Bases: M_Operation[GeneralRegisterType]

Decrements the value at the memory location pointed to by m. [x[m]] = [x[m]] - 1

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_DecOp(M_Operation[GeneralRegisterType]):
    """
    Decrements the value at the memory location pointed to by m.
    [x[m]] = [x[m]] - 1

    See external [documentation](https://www.felixcloutier.com/x86/dec).
    """

    name = "x86.m.dec"

name = 'x86.m.dec' class-attribute instance-attribute

M_IDivOp

Bases: X86Instruction

Divides the value in RDX:RAX by [m] and stores the quotient in RAX and the remainder in RDX.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_IDivOp(X86Instruction):
    """
    Divides the value in RDX:RAX by [m] and stores the quotient in RAX and the remainder in RDX.

    See external [documentation](https://www.felixcloutier.com/x86/idiv).
    """

    name = "x86.m.idiv"

    memory = operand_def(X86RegisterType)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))
    rdx_in = operand_def(RDX)
    rdx_out = result_def(RDX)
    rax_in = operand_def(RAX)
    rax_out = result_def(RAX)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $rdx_in `,` $rax_in attr-dict `:` "
        "`(` type($memory) `,` type($rdx_in) `,` type($rax_in) `)` "
        "`->` `(` type($rdx_out) `,` type($rax_out) `)`"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        rdx_in: Operation | SSAValue,
        rax_in: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        comment: str | StringAttr | None = None,
        rdx_out: GeneralRegisterType,
        rax_out: GeneralRegisterType,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory, rdx_in, rax_in],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[rdx_out, rax_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return (memory_access,)

name = 'x86.m.idiv' class-attribute instance-attribute

memory = operand_def(X86RegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

rdx_in = operand_def(RDX) class-attribute instance-attribute

rdx_out = result_def(RDX) class-attribute instance-attribute

rax_in = operand_def(RAX) class-attribute instance-attribute

rax_out = result_def(RAX) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $rdx_in `,` $rax_in attr-dict `:` `(` type($memory) `,` type($rdx_in) `,` type($rax_in) `)` `->` `(` type($rdx_out) `,` type($rax_out) `)`' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, rdx_in: Operation | SSAValue, rax_in: Operation | SSAValue, memory_offset: int | IntegerAttr, *, comment: str | StringAttr | None = None, rdx_out: GeneralRegisterType, rax_out: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    rdx_in: Operation | SSAValue,
    rax_in: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    comment: str | StringAttr | None = None,
    rdx_out: GeneralRegisterType,
    rax_out: GeneralRegisterType,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory, rdx_in, rax_in],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[rdx_out, rax_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return (memory_access,)

M_ImulOp

Bases: X86Instruction

The source operand is multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers. x[RDX:RAX] = x[RAX] * [x[m]]

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class M_ImulOp(X86Instruction):
    """
    The source operand is multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.
    x[RDX:RAX] = x[RAX] * [x[m]]

    See external [documentation](https://www.felixcloutier.com/x86/imul).
    """

    name = "x86.m.imul"

    memory = operand_def(GeneralRegisterType)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))

    rdx_out = result_def(RDX)
    rax_in = operand_def(RAX)
    rax_out = result_def(RAX)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $rax_in attr-dict `:` "
        "`(` type($memory) `,` type($rax_in) `)` "
        "`->` `(` type($rdx_out) `,` type($rax_out) `)`"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        rax_in: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        comment: str | StringAttr | None = None,
        rdx_out: GeneralRegisterType,
        rax_out: GeneralRegisterType,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory, rax_in],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[rdx_out, rax_out],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return (memory_access,)

name = 'x86.m.imul' class-attribute instance-attribute

memory = operand_def(GeneralRegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

rdx_out = result_def(RDX) class-attribute instance-attribute

rax_in = operand_def(RAX) class-attribute instance-attribute

rax_out = result_def(RAX) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $rax_in attr-dict `:` `(` type($memory) `,` type($rax_in) `)` `->` `(` type($rdx_out) `,` type($rax_out) `)`' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, rax_in: Operation | SSAValue, memory_offset: int | IntegerAttr, *, comment: str | StringAttr | None = None, rdx_out: GeneralRegisterType, rax_out: GeneralRegisterType)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    rax_in: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    comment: str | StringAttr | None = None,
    rdx_out: GeneralRegisterType,
    rax_out: GeneralRegisterType,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory, rax_in],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[rdx_out, rax_out],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return (memory_access,)

LabelOp

Bases: X86AsmOperation, X86HasRegisterConstraints

The label operation is used to emit text labels (e.g. loop:) that are used as branch, unconditional jump targets and symbol offsets.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class LabelOp(X86AsmOperation, X86HasRegisterConstraints):
    """
    The label operation is used to emit text labels (e.g. loop:) that are used
    as branch, unconditional jump targets and symbol offsets.
    """

    name = "x86.label"
    label = attr_def(StringAttr)
    comment = opt_attr_def(StringAttr)

    assembly_format = "$label attr-dict"

    def __init__(
        self,
        label: str | StringAttr,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(label, str):
            label = StringAttr(label)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            attributes={
                "label": label,
                "comment": comment,
            },
        )

    def assembly_line(self) -> str | None:
        return AssemblyPrinter.append_comment(f"{self.label.data}:", self.comment)

name = 'x86.label' class-attribute instance-attribute

label = attr_def(StringAttr) class-attribute instance-attribute

comment = opt_attr_def(StringAttr) class-attribute instance-attribute

assembly_format = '$label attr-dict' class-attribute instance-attribute

__init__(label: str | StringAttr, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    label: str | StringAttr,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(label, str):
        label = StringAttr(label)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        attributes={
            "label": label,
            "comment": comment,
        },
    )

assembly_line() -> str | None

Source code in xdsl/dialects/x86/ops.py

def assembly_line(self) -> str | None:
    return AssemblyPrinter.append_comment(f"{self.label.data}:", self.comment)

DirectiveOp

Bases: X86AsmOperation, X86HasRegisterConstraints, X86CustomFormatOperation

The directive operation is used to represent a directive in the assembly code. (e.g. .globl; .type etc)

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DirectiveOp(X86AsmOperation, X86HasRegisterConstraints, X86CustomFormatOperation):
    """
    The directive operation is used to represent a directive in the assembly code. (e.g. .globl; .type etc)
    """

    name = "x86.directive"

    directive = attr_def(StringAttr)
    value = opt_attr_def(StringAttr)

    def __init__(
        self,
        directive: str | StringAttr,
        value: str | StringAttr | None,
    ):
        if isinstance(directive, str):
            directive = StringAttr(directive)
        if isinstance(value, str):
            value = StringAttr(value)

        super().__init__(
            attributes={
                "directive": directive,
                "value": value,
            },
        )

    def assembly_line(self) -> str | None:
        if self.value is not None and self.value.data:
            arg_str = assembly_arg_str(self.value.data)
        else:
            arg_str = ""

        return AssemblyPrinter.assembly_line(
            self.directive.data, arg_str, is_indented=False
        )

    @classmethod
    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
        attributes = dict[str, Attribute]()
        attributes["directive"] = StringAttr(
            parser.parse_str_literal("Expected directive")
        )
        if (value := parser.parse_optional_str_literal()) is not None:
            attributes["value"] = StringAttr(value)
        return attributes

    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
        printer.print_string(" ")
        printer.print_string_literal(self.directive.data)
        if self.value is not None:
            printer.print_string(" ")
            printer.print_string_literal(self.value.data)
        return {"directive", "value"}

    def print_op_type(self, printer: Printer) -> None:
        return

    @classmethod
    def parse_op_type(
        cls, parser: Parser
    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
        return (), ()

name = 'x86.directive' class-attribute instance-attribute

directive = attr_def(StringAttr) class-attribute instance-attribute

value = opt_attr_def(StringAttr) class-attribute instance-attribute

__init__(directive: str | StringAttr, value: str | StringAttr | None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    directive: str | StringAttr,
    value: str | StringAttr | None,
):
    if isinstance(directive, str):
        directive = StringAttr(directive)
    if isinstance(value, str):
        value = StringAttr(value)

    super().__init__(
        attributes={
            "directive": directive,
            "value": value,
        },
    )

assembly_line() -> str | None

Source code in xdsl/dialects/x86/ops.py

def assembly_line(self) -> str | None:
    if self.value is not None and self.value.data:
        arg_str = assembly_arg_str(self.value.data)
    else:
        arg_str = ""

    return AssemblyPrinter.assembly_line(
        self.directive.data, arg_str, is_indented=False
    )

custom_parse_attributes(parser: Parser) -> dict[str, Attribute] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
    attributes = dict[str, Attribute]()
    attributes["directive"] = StringAttr(
        parser.parse_str_literal("Expected directive")
    )
    if (value := parser.parse_optional_str_literal()) is not None:
        attributes["value"] = StringAttr(value)
    return attributes

custom_print_attributes(printer: Printer) -> AbstractSet[str]

Source code in xdsl/dialects/x86/ops.py

def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
    printer.print_string(" ")
    printer.print_string_literal(self.directive.data)
    if self.value is not None:
        printer.print_string(" ")
        printer.print_string_literal(self.value.data)
    return {"directive", "value"}

print_op_type(printer: Printer) -> None

Source code in xdsl/dialects/x86/ops.py

def print_op_type(self, printer: Printer) -> None:
    return

parse_op_type(parser: Parser) -> tuple[Sequence[Attribute], Sequence[Attribute]] classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse_op_type(
    cls, parser: Parser
) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
    return (), ()

C_JmpOp

Bases: X86Instruction, X86CustomFormatOperation

Unconditional jump to the label specified in destination.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JmpOp(X86Instruction, X86CustomFormatOperation):
    """
    Unconditional jump to the label specified in destination.

    See external [documentation](https://www.felixcloutier.com/x86/jmp).
    """

    name = "x86.c.jmp"

    block_values = var_operand_def(X86RegisterType)

    successor = successor_def()

    traits = traits_def(IsTerminator())

    def __init__(
        self,
        block_values: Sequence[SSAValue],
        successor: Successor,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[block_values],
            attributes={
                "comment": comment,
            },
            successors=(successor,),
        )

    def verify_(self) -> None:
        # Types of arguments must match arg types of blocks

        for op_arg, block_arg in zip(self.block_values, self.successor.args):
            if op_arg.type != block_arg.type:
                raise VerifyException(
                    f"Block arg types must match {op_arg.type} {block_arg.type}"
                )

        if not isinstance(self.successor.first_op, LabelOp):
            raise VerifyException(
                "jmp operation successor must have a x86.label operation as a "
                f"first argument, found {self.successor.first_op}"
            )

    def print(self, printer: Printer) -> None:
        printer.print_string(" ")
        printer.print_block_name(self.successor)
        printer.print_string("(")
        printer.print_list(self.block_values, lambda val: print_type_pair(printer, val))
        printer.print_string(")")
        if self.attributes:
            printer.print_op_attributes(self.attributes, print_keyword=True)

    @classmethod
    def parse(cls, parser: Parser) -> Self:
        successor = parser.parse_successor()
        block_values = parser.parse_comma_separated_list(
            parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
        )
        attrs = parser.parse_optional_attr_dict_with_keyword()
        op = cls(block_values, successor)
        if attrs is not None:
            op.attributes |= attrs.data
        return op

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        dest_label = self.successor.first_op
        assert isinstance(dest_label, LabelOp)
        dest_label_str = dest_label.label.data
        if dest_label_str.isdigit():
            # x86 Assembly: Numeric jump labels must be annotated with a suffix.
            # Jumping backward in code requires appending 'b' (e.g., "1b"), and
            # jumping forward requires appending 'f' (e.g., "1f").
            # Proper support for generating these labels is currently unimplemented.
            raise NotImplementedError(
                "Assembly printing for jumps to numeric labels not implemented"
            )
        return (dest_label_str,)

name = 'x86.c.jmp' class-attribute instance-attribute

block_values = var_operand_def(X86RegisterType) class-attribute instance-attribute

successor = successor_def() class-attribute instance-attribute

traits = traits_def(IsTerminator()) class-attribute instance-attribute

__init__(block_values: Sequence[SSAValue], successor: Successor, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    block_values: Sequence[SSAValue],
    successor: Successor,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[block_values],
        attributes={
            "comment": comment,
        },
        successors=(successor,),
    )

verify_() -> None

Source code in xdsl/dialects/x86/ops.py

def verify_(self) -> None:
    # Types of arguments must match arg types of blocks

    for op_arg, block_arg in zip(self.block_values, self.successor.args):
        if op_arg.type != block_arg.type:
            raise VerifyException(
                f"Block arg types must match {op_arg.type} {block_arg.type}"
            )

    if not isinstance(self.successor.first_op, LabelOp):
        raise VerifyException(
            "jmp operation successor must have a x86.label operation as a "
            f"first argument, found {self.successor.first_op}"
        )

print(printer: Printer) -> None

Source code in xdsl/dialects/x86/ops.py

def print(self, printer: Printer) -> None:
    printer.print_string(" ")
    printer.print_block_name(self.successor)
    printer.print_string("(")
    printer.print_list(self.block_values, lambda val: print_type_pair(printer, val))
    printer.print_string(")")
    if self.attributes:
        printer.print_op_attributes(self.attributes, print_keyword=True)

parse(parser: Parser) -> Self classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse(cls, parser: Parser) -> Self:
    successor = parser.parse_successor()
    block_values = parser.parse_comma_separated_list(
        parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
    )
    attrs = parser.parse_optional_attr_dict_with_keyword()
    op = cls(block_values, successor)
    if attrs is not None:
        op.attributes |= attrs.data
    return op

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    dest_label = self.successor.first_op
    assert isinstance(dest_label, LabelOp)
    dest_label_str = dest_label.label.data
    if dest_label_str.isdigit():
        # x86 Assembly: Numeric jump labels must be annotated with a suffix.
        # Jumping backward in code requires appending 'b' (e.g., "1b"), and
        # jumping forward requires appending 'f' (e.g., "1f").
        # Proper support for generating these labels is currently unimplemented.
        raise NotImplementedError(
            "Assembly printing for jumps to numeric labels not implemented"
        )
    return (dest_label_str,)

FallthroughOp

Bases: X86AsmOperation, X86HasRegisterConstraints, X86CustomFormatOperation

Continue execution into the next block. The successor of this operation must be immediately after this operation's parent.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class FallthroughOp(
    X86AsmOperation, X86HasRegisterConstraints, X86CustomFormatOperation
):
    """
    Continue execution into the next block.
    The successor of this operation must be immediately after this operation's parent.
    """

    name = "x86.fallthrough"

    block_values = var_operand_def(X86RegisterType)

    successor = successor_def()

    traits = traits_def(IsTerminator(), NoMemoryEffect())

    def __init__(
        self,
        block_values: Sequence[SSAValue],
        successor: Successor,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[block_values],
            attributes={
                "comment": comment,
            },
            successors=(successor,),
        )

    def verify_(self) -> None:
        # Types of arguments must match arg types of blocks

        for op_arg, block_arg in zip(self.block_values, self.successor.args):
            if op_arg.type != block_arg.type:
                raise VerifyException(
                    f"Block arg types must match {op_arg.type} {block_arg.type}"
                )

        if (parent := self.parent) is not None:
            if parent.next_block is not self.successor:
                raise VerifyException(
                    "Fallthrough op successor must immediately follow its parent."
                )

    def print(self, printer: Printer) -> None:
        printer.print_string(" ")
        printer.print_block_name(self.successor)
        printer.print_string("(")
        printer.print_list(self.block_values, lambda val: print_type_pair(printer, val))
        printer.print_string(")")
        if self.attributes:
            printer.print_op_attributes(self.attributes, print_keyword=True)

    @classmethod
    def parse(cls, parser: Parser) -> Self:
        successor = parser.parse_successor()
        block_values = parser.parse_comma_separated_list(
            parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
        )
        attrs = parser.parse_optional_attr_dict_with_keyword()
        op = cls(block_values, successor)
        if attrs is not None:
            op.attributes |= attrs.data
        return op

    def assembly_line(self) -> str | None:
        # Not printed in assembly
        return None

name = 'x86.fallthrough' class-attribute instance-attribute

block_values = var_operand_def(X86RegisterType) class-attribute instance-attribute

successor = successor_def() class-attribute instance-attribute

traits = traits_def(IsTerminator(), NoMemoryEffect()) class-attribute instance-attribute

__init__(block_values: Sequence[SSAValue], successor: Successor, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    block_values: Sequence[SSAValue],
    successor: Successor,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[block_values],
        attributes={
            "comment": comment,
        },
        successors=(successor,),
    )

verify_() -> None

Source code in xdsl/dialects/x86/ops.py

def verify_(self) -> None:
    # Types of arguments must match arg types of blocks

    for op_arg, block_arg in zip(self.block_values, self.successor.args):
        if op_arg.type != block_arg.type:
            raise VerifyException(
                f"Block arg types must match {op_arg.type} {block_arg.type}"
            )

    if (parent := self.parent) is not None:
        if parent.next_block is not self.successor:
            raise VerifyException(
                "Fallthrough op successor must immediately follow its parent."
            )

print(printer: Printer) -> None

Source code in xdsl/dialects/x86/ops.py

def print(self, printer: Printer) -> None:
    printer.print_string(" ")
    printer.print_block_name(self.successor)
    printer.print_string("(")
    printer.print_list(self.block_values, lambda val: print_type_pair(printer, val))
    printer.print_string(")")
    if self.attributes:
        printer.print_op_attributes(self.attributes, print_keyword=True)

parse(parser: Parser) -> Self classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def parse(cls, parser: Parser) -> Self:
    successor = parser.parse_successor()
    block_values = parser.parse_comma_separated_list(
        parser.Delimiter.PAREN, lambda: parse_type_pair(parser)
    )
    attrs = parser.parse_optional_attr_dict_with_keyword()
    op = cls(block_values, successor)
    if attrs is not None:
        op.attributes |= attrs.data
    return op

assembly_line() -> str | None

Source code in xdsl/dialects/x86/ops.py

def assembly_line(self) -> str | None:
    # Not printed in assembly
    return None

SS_CmpOp

Bases: X86Instruction

Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class SS_CmpOp(X86Instruction):
    """
    Compares the first source operand with the second source operand and sets the status
    flags in the EFLAGS register according to the results.

    See external [documentation](https://www.felixcloutier.com/x86/cmp).
    """

    name = "x86.ss.cmp"

    source1 = operand_def(X86RegisterType)
    source2 = operand_def(X86RegisterType)

    result = result_def(RFLAGS)

    assembly_format = (
        "$source1 `,` $source2 attr-dict `:` "
        "`(` type($source1) `,` type($source2) `)` `->` type($result)"
    )

    def __init__(
        self,
        source1: Operation | SSAValue,
        source2: Operation | SSAValue,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source1, source2],
            attributes={
                "comment": comment,
            },
            result_types=[RFLAGS],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        return reg(self.source1), reg(self.source2)

name = 'x86.ss.cmp' class-attribute instance-attribute

source1 = operand_def(X86RegisterType) class-attribute instance-attribute

source2 = operand_def(X86RegisterType) class-attribute instance-attribute

result = result_def(RFLAGS) class-attribute instance-attribute

assembly_format = '$source1 `,` $source2 attr-dict `:` `(` type($source1) `,` type($source2) `)` `->` type($result)' class-attribute instance-attribute

__init__(source1: Operation | SSAValue, source2: Operation | SSAValue, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source1: Operation | SSAValue,
    source2: Operation | SSAValue,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source1, source2],
        attributes={
            "comment": comment,
        },
        result_types=[RFLAGS],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    return reg(self.source1), reg(self.source2)

SM_CmpOp

Bases: X86Instruction

Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class SM_CmpOp(X86Instruction):
    """
    Compares the first source operand with the second source operand and sets the status
    flags in the EFLAGS register according to the results.

    See external [documentation](https://www.felixcloutier.com/x86/cmp).
    """

    name = "x86.sm.cmp"

    source = operand_def(GeneralRegisterType)
    memory = operand_def(GeneralRegisterType)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))

    result = result_def(RFLAGS)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "$source `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` "
        "`(` type($source) `,` type($memory) `)` `->` type($result)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source, memory],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[RFLAGS],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return reg(self.source), memory_access

name = 'x86.sm.cmp' class-attribute instance-attribute

source = operand_def(GeneralRegisterType) class-attribute instance-attribute

memory = operand_def(GeneralRegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

result = result_def(RFLAGS) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '$source `,` `[` $memory (`+` $memory_offset^)? `]` attr-dict `:` `(` type($source) `,` type($memory) `)` `->` type($result)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, memory: Operation | SSAValue, memory_offset: int | IntegerAttr, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source, memory],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[RFLAGS],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return reg(self.source), memory_access

SI_CmpOp

Bases: X86Instruction

Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class SI_CmpOp(X86Instruction):
    """
    Compares the first source operand with the second source operand and sets the status
    flags in the EFLAGS register according to the results.

    See external [documentation](https://www.felixcloutier.com/x86/cmp).
    """

    name = "x86.si.cmp"

    source = operand_def(GeneralRegisterType)
    immediate = attr_def(IntegerAttr[SI32])

    result = result_def(RFLAGS)

    assembly_format = (
        "$source `,` $immediate attr-dict `:` `(` type($source) `)` `->` type($result)"
    )

    def __init__(
        self,
        source: Operation | SSAValue,
        immediate: int | IntegerAttr[SI32],
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[source],
            attributes={
                "immediate": immediate,
                "comment": comment,
            },
            result_types=[RFLAGS],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
        return reg(self.source), self.immediate

name = 'x86.si.cmp' class-attribute instance-attribute

source = operand_def(GeneralRegisterType) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

result = result_def(RFLAGS) class-attribute instance-attribute

assembly_format = '$source `,` $immediate attr-dict `:` `(` type($source) `)` `->` type($result)' class-attribute instance-attribute

__init__(source: Operation | SSAValue, immediate: int | IntegerAttr[SI32], *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    source: Operation | SSAValue,
    immediate: int | IntegerAttr[SI32],
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[source],
        attributes={
            "immediate": immediate,
            "comment": comment,
        },
        result_types=[RFLAGS],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
    return reg(self.source), self.immediate

MS_CmpOp

Bases: X86Instruction

Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_CmpOp(X86Instruction):
    """
    Compares the first source operand with the second source operand and sets the status
    flags in the EFLAGS register according to the results.

    See external [documentation](https://www.felixcloutier.com/x86/cmp).
    """

    name = "x86.ms.cmp"

    memory = operand_def(GeneralRegisterType)
    memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64))
    source = operand_def(GeneralRegisterType)

    result = result_def(RFLAGS)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $source attr-dict `:` "
        "`(` type($memory) `,` type($source) `)` `->` type($result)"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        source: Operation | SSAValue,
        memory_offset: int | IntegerAttr,
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, i64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory, source],
            attributes={
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[RFLAGS],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return memory_access, reg(self.source)

name = 'x86.ms.cmp' class-attribute instance-attribute

memory = operand_def(GeneralRegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[I64], default_value=IntegerAttr(0, i64)) class-attribute instance-attribute

source = operand_def(GeneralRegisterType) class-attribute instance-attribute

result = result_def(RFLAGS) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $source attr-dict `:` `(` type($memory) `,` type($source) `)` `->` type($result)' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, source: Operation | SSAValue, memory_offset: int | IntegerAttr, *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    source: Operation | SSAValue,
    memory_offset: int | IntegerAttr,
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, i64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory, source],
        attributes={
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[RFLAGS],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return memory_access, reg(self.source)

MI_CmpOp

Bases: X86Instruction

Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MI_CmpOp(X86Instruction):
    """
    Compares the first source operand with the second source operand and sets the status
    flags in the EFLAGS register according to the results.

    See external [documentation](https://www.felixcloutier.com/x86/cmp).
    """

    name = "x86.mi.cmp"

    memory = operand_def(GeneralRegisterType)
    memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64))
    immediate = attr_def(IntegerAttr[SI32])

    result = result_def(RFLAGS)

    traits = traits_def(MemoryReadEffect())

    assembly_format = (
        "` ` `[` $memory (`+` $memory_offset^)? `]` `,` $immediate attr-dict `:`"
        "type($memory) `->` type($result)"
    )

    def __init__(
        self,
        memory: Operation | SSAValue,
        memory_offset: int | IntegerAttr[SI64],
        immediate: int | IntegerAttr[SI32],
        *,
        comment: str | StringAttr | None = None,
    ):
        if isinstance(immediate, int):
            immediate = IntegerAttr(immediate, si32)
        if isinstance(memory_offset, int):
            memory_offset = IntegerAttr(memory_offset, si64)
        if isinstance(comment, str):
            comment = StringAttr(comment)

        super().__init__(
            operands=[memory],
            attributes={
                "immediate": immediate,
                "memory_offset": memory_offset,
                "comment": comment,
            },
            result_types=[RFLAGS],
        )

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        immediate = assembly_arg_str(self.immediate)
        memory_access = memory_access_str(self.memory, self.memory_offset)
        return memory_access, immediate

name = 'x86.mi.cmp' class-attribute instance-attribute

memory = operand_def(GeneralRegisterType) class-attribute instance-attribute

memory_offset = attr_def(IntegerAttr[SI64], default_value=IntegerAttr(0, si64)) class-attribute instance-attribute

immediate = attr_def(IntegerAttr[SI32]) class-attribute instance-attribute

result = result_def(RFLAGS) class-attribute instance-attribute

traits = traits_def(MemoryReadEffect()) class-attribute instance-attribute

assembly_format = '` ` `[` $memory (`+` $memory_offset^)? `]` `,` $immediate attr-dict `:`type($memory) `->` type($result)' class-attribute instance-attribute

__init__(memory: Operation | SSAValue, memory_offset: int | IntegerAttr[SI64], immediate: int | IntegerAttr[SI32], *, comment: str | StringAttr | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    memory: Operation | SSAValue,
    memory_offset: int | IntegerAttr[SI64],
    immediate: int | IntegerAttr[SI32],
    *,
    comment: str | StringAttr | None = None,
):
    if isinstance(immediate, int):
        immediate = IntegerAttr(immediate, si32)
    if isinstance(memory_offset, int):
        memory_offset = IntegerAttr(memory_offset, si64)
    if isinstance(comment, str):
        comment = StringAttr(comment)

    super().__init__(
        operands=[memory],
        attributes={
            "immediate": immediate,
            "memory_offset": memory_offset,
            "comment": comment,
        },
        result_types=[RFLAGS],
    )

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    immediate = assembly_arg_str(self.immediate)
    memory_access = memory_access_str(self.memory, self.memory_offset)
    return memory_access, immediate

C_JaOp dataclass

Bases: ConditionalJumpOperation

Jump if above (CF=0 and ZF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JaOp(ConditionalJumpOperation):
    """
    Jump if above (CF=0 and ZF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.ja"

name = 'x86.c.ja' class-attribute instance-attribute

C_JaeOp dataclass

Bases: ConditionalJumpOperation

Jump if above or equal (CF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JaeOp(ConditionalJumpOperation):
    """
    Jump if above or equal (CF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jae"

name = 'x86.c.jae' class-attribute instance-attribute

C_JbOp dataclass

Bases: ConditionalJumpOperation

Jump if below (CF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JbOp(ConditionalJumpOperation):
    """
    Jump if below (CF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jb"

name = 'x86.c.jb' class-attribute instance-attribute

C_JbeOp dataclass

Bases: ConditionalJumpOperation

Jump if below or equal (CF=1 or ZF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JbeOp(ConditionalJumpOperation):
    """
    Jump if below or equal (CF=1 or ZF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jbe"

name = 'x86.c.jbe' class-attribute instance-attribute

C_JcOp dataclass

Bases: ConditionalJumpOperation

Jump if carry (CF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JcOp(ConditionalJumpOperation):
    """
    Jump if carry (CF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jc"

name = 'x86.c.jc' class-attribute instance-attribute

C_JeOp dataclass

Bases: ConditionalJumpOperation

Jump if equal (ZF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JeOp(ConditionalJumpOperation):
    """
    Jump if equal (ZF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.je"

name = 'x86.c.je' class-attribute instance-attribute

C_JgOp dataclass

Bases: ConditionalJumpOperation

Jump if greater (ZF=0 and SF=OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JgOp(ConditionalJumpOperation):
    """
    Jump if greater (ZF=0 and SF=OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jg"

name = 'x86.c.jg' class-attribute instance-attribute

C_JgeOp dataclass

Bases: ConditionalJumpOperation

Jump if greater or equal (SF=OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JgeOp(ConditionalJumpOperation):
    """
    Jump if greater or equal (SF=OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jge"

name = 'x86.c.jge' class-attribute instance-attribute

C_JlOp dataclass

Bases: ConditionalJumpOperation

Jump if less (SF≠OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JlOp(ConditionalJumpOperation):
    """
    Jump if less (SF≠OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jl"

name = 'x86.c.jl' class-attribute instance-attribute

C_JleOp dataclass

Bases: ConditionalJumpOperation

Jump if less or equal (ZF=1 or SF≠OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JleOp(ConditionalJumpOperation):
    """
    Jump if less or equal (ZF=1 or SF≠OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jle"

name = 'x86.c.jle' class-attribute instance-attribute

C_JnaOp dataclass

Bases: ConditionalJumpOperation

Jump if not above (CF=1 or ZF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnaOp(ConditionalJumpOperation):
    """
    Jump if not above (CF=1 or ZF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jna"

name = 'x86.c.jna' class-attribute instance-attribute

C_JnaeOp dataclass

Bases: ConditionalJumpOperation

Jump if not above or equal (CF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnaeOp(ConditionalJumpOperation):
    """
    Jump if not above or equal (CF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnae"

name = 'x86.c.jnae' class-attribute instance-attribute

C_JnbOp dataclass

Bases: ConditionalJumpOperation

Jump if not below (CF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnbOp(ConditionalJumpOperation):
    """
    Jump if not below (CF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnb"

name = 'x86.c.jnb' class-attribute instance-attribute

C_JnbeOp dataclass

Bases: ConditionalJumpOperation

Jump if not below or equal (CF=0 and ZF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnbeOp(ConditionalJumpOperation):
    """
    Jump if not below or equal (CF=0 and ZF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnbe"

name = 'x86.c.jnbe' class-attribute instance-attribute

C_JncOp dataclass

Bases: ConditionalJumpOperation

Jump if not carry (CF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JncOp(ConditionalJumpOperation):
    """
    Jump if not carry (CF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnc"

name = 'x86.c.jnc' class-attribute instance-attribute

C_JneOp dataclass

Bases: ConditionalJumpOperation

Jump if not equal (ZF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JneOp(ConditionalJumpOperation):
    """
    Jump if not equal (ZF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jne"

name = 'x86.c.jne' class-attribute instance-attribute

C_JngOp dataclass

Bases: ConditionalJumpOperation

Jump if not greater (ZF=1 or SF≠OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JngOp(ConditionalJumpOperation):
    """
    Jump if not greater (ZF=1 or SF≠OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jng"

name = 'x86.c.jng' class-attribute instance-attribute

C_JngeOp dataclass

Bases: ConditionalJumpOperation

Jump if not greater or equal (SF≠OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JngeOp(ConditionalJumpOperation):
    """
    Jump if not greater or equal (SF≠OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnge"

name = 'x86.c.jnge' class-attribute instance-attribute

C_JnlOp dataclass

Bases: ConditionalJumpOperation

Jump if not less (SF=OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnlOp(ConditionalJumpOperation):
    """
    Jump if not less (SF=OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnl"

name = 'x86.c.jnl' class-attribute instance-attribute

C_JnleOp dataclass

Bases: ConditionalJumpOperation

Jump if not less or equal (ZF=0 and SF=OF).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnleOp(ConditionalJumpOperation):
    """
    Jump if not less or equal (ZF=0 and SF=OF).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnle"

name = 'x86.c.jnle' class-attribute instance-attribute

C_JnoOp dataclass

Bases: ConditionalJumpOperation

Jump if not overflow (OF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnoOp(ConditionalJumpOperation):
    """
    Jump if not overflow (OF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jno"

name = 'x86.c.jno' class-attribute instance-attribute

C_JnpOp dataclass

Bases: ConditionalJumpOperation

Jump if not parity (PF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnpOp(ConditionalJumpOperation):
    """
    Jump if not parity (PF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnp"

name = 'x86.c.jnp' class-attribute instance-attribute

C_JnsOp dataclass

Bases: ConditionalJumpOperation

Jump if not sign (SF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnsOp(ConditionalJumpOperation):
    """
    Jump if not sign (SF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jns"

name = 'x86.c.jns' class-attribute instance-attribute

C_JnzOp dataclass

Bases: ConditionalJumpOperation

Jump if not zero (ZF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JnzOp(ConditionalJumpOperation):
    """
    Jump if not zero (ZF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jnz"

name = 'x86.c.jnz' class-attribute instance-attribute

C_JoOp dataclass

Bases: ConditionalJumpOperation

Jump if overflow (OF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JoOp(ConditionalJumpOperation):
    """
    Jump if overflow (OF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jo"

name = 'x86.c.jo' class-attribute instance-attribute

C_JpOp dataclass

Bases: ConditionalJumpOperation

Jump if parity (PF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JpOp(ConditionalJumpOperation):
    """
    Jump if parity (PF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jp"

name = 'x86.c.jp' class-attribute instance-attribute

C_JpeOp dataclass

Bases: ConditionalJumpOperation

Jump if parity even (PF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JpeOp(ConditionalJumpOperation):
    """
    Jump if parity even (PF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jpe"

name = 'x86.c.jpe' class-attribute instance-attribute

C_JpoOp dataclass

Bases: ConditionalJumpOperation

Jump if parity odd (PF=0).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JpoOp(ConditionalJumpOperation):
    """
    Jump if parity odd (PF=0).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jpo"

name = 'x86.c.jpo' class-attribute instance-attribute

C_JsOp dataclass

Bases: ConditionalJumpOperation

Jump if sign (SF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JsOp(ConditionalJumpOperation):
    """
    Jump if sign (SF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.js"

name = 'x86.c.js' class-attribute instance-attribute

C_JzOp dataclass

Bases: ConditionalJumpOperation

Jump if zero (ZF=1).

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class C_JzOp(ConditionalJumpOperation):
    """
    Jump if zero (ZF=1).

    See external [documentation](https://www.felixcloutier.com/x86/jcc).
    """

    name = "x86.c.jz"

name = 'x86.c.jz' class-attribute instance-attribute

RSS_Vfmadd231pdOp dataclass

Bases: RSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Multiply packed double-precision floating-point elements in s1 and s2, add the intermediate result to r, and store the final result in r.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RSS_Vfmadd231pdOp(
    RSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Multiply packed double-precision floating-point elements in s1 and s2, add the
    intermediate result to r, and store the final result in r.

    See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
    """

    name = "x86.rss.vfmadd231pd"

name = 'x86.rss.vfmadd231pd' class-attribute instance-attribute

RSSK_Vfmadd231pdOp dataclass

Bases: RSSK_Operation

AVX512 masked multiply packed double-precision floating-point elements in s1 and s2, add the intermediate result to r, and store the final result in r.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RSSK_Vfmadd231pdOp(RSSK_Operation):
    """
    AVX512 masked multiply packed double-precision floating-point elements in s1 and s2, add the
    intermediate result to r, and store the final result in r.

    See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
    """

    name = "x86.rssk.vfmadd231pd"

name = 'x86.rssk.vfmadd231pd' class-attribute instance-attribute

RSM_Vfmadd231pdOp dataclass

Bases: RSMB_Operation[X86VectorRegisterType, X86VectorRegisterType, GeneralRegisterType]

Multiply packed double-precision floating-point elements in s1 and at specified memory location, add the intermediate result to r, and store the final result in r.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RSM_Vfmadd231pdOp(
    RSMB_Operation[X86VectorRegisterType, X86VectorRegisterType, GeneralRegisterType]
):
    """
    Multiply packed double-precision floating-point elements in s1 and at specified memory location, add the
    intermediate result to r, and store the final result in r.

    See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
    """

    name = "x86.rsm.vfmadd231pd"

    @classmethod
    def lane_bitwidth(cls) -> int:
        return 64

name = 'x86.rsm.vfmadd231pd' class-attribute instance-attribute

lane_bitwidth() -> int classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def lane_bitwidth(cls) -> int:
    return 64

RSS_Vfmadd231psOp dataclass

Bases: RSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Multiply packed single-precision floating-point elements in s1 and s2, add the intermediate result to r, and store the final result in r.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RSS_Vfmadd231psOp(
    RSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Multiply packed single-precision floating-point elements in s1 and s2, add the
    intermediate result to r, and store the final result in r.

    See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
    """

    name = "x86.rss.vfmadd231ps"

name = 'x86.rss.vfmadd231ps' class-attribute instance-attribute

RSM_Vfmadd231psOp dataclass

Bases: RSMB_Operation[X86VectorRegisterType, X86VectorRegisterType, GeneralRegisterType]

Multiply packed single-precision floating-point elements in s1 and at specified memory location, add the intermediate result to r, and store the final result in r.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class RSM_Vfmadd231psOp(
    RSMB_Operation[X86VectorRegisterType, X86VectorRegisterType, GeneralRegisterType]
):
    """
    Multiply packed single-precision floating-point elements in s1 and at specified memory location, add the
    intermediate result to r, and store the final result in r.

    See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
    """

    name = "x86.rsm.vfmadd231ps"

    @classmethod
    def lane_bitwidth(cls) -> int:
        return 32

name = 'x86.rsm.vfmadd231ps' class-attribute instance-attribute

lane_bitwidth() -> int classmethod

Source code in xdsl/dialects/x86/ops.py

@classmethod
def lane_bitwidth(cls) -> int:
    return 32

DSM_VmulpdOp dataclass

Bases: DSM_Operation[X86VectorRegisterType, X86VectorRegisterType, GeneralRegisterType]

Multiply packed double-precision floating-point elements in s and at the specified memory location and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSM_VmulpdOp(
    DSM_Operation[X86VectorRegisterType, X86VectorRegisterType, GeneralRegisterType]
):
    """
    Multiply packed double-precision floating-point elements in s and at the specified
    memory location and store the result in d.

    See external [documentation](https://www.felixcloutier.com/x86/mulpd).
    """

    name = "x86.dsm.vmulpd"

    def verify_(self) -> None:
        _verify_same_vector_width(self.destination, self.source)

name = 'x86.dsm.vmulpd' class-attribute instance-attribute

verify_() -> None

Source code in xdsl/dialects/x86/ops.py

def verify_(self) -> None:
    _verify_same_vector_width(self.destination, self.source)

DSS_AddpdOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Add packed double-precision floating-point elements in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_AddpdOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Add packed double-precision floating-point elements in s1 and s2 and store the
    result in d.

    See external [documentation](https://www.felixcloutier.com/x86/addpd).
    """

    name = "x86.dss.addpd"

name = 'x86.dss.addpd' class-attribute instance-attribute

DSS_AddpsOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Add packed single-precision floating-point elements in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_AddpsOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Add packed single-precision floating-point elements in s1 and s2 and store the
    result in d.

    See external [documentation](https://www.felixcloutier.com/x86/addps).
    """

    name = "x86.dss.addps"

name = 'x86.dss.addps' class-attribute instance-attribute

DSS_VaddpdOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Add packed double-precision floating-point elements in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_VaddpdOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Add packed double-precision floating-point elements in s1 and s2 and store the
    result in d.

    See external [documentation](https://www.felixcloutier.com/x86/addpd).
    """

    name = "x86.dss.vaddpd"

name = 'x86.dss.vaddpd' class-attribute instance-attribute

DSM_VaddsdOp dataclass

Bases: DSM_Operation[SSERegisterType, SSERegisterType, GeneralRegisterType]

Add the low double-precision floating-point elements in s and at the specified memory location and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSM_VaddsdOp(
    DSM_Operation[SSERegisterType, SSERegisterType, GeneralRegisterType]
):
    """
    Add the low double-precision floating-point elements in s and at the specified
    memory location and store the result in d.

    See external [documentation](https://www.felixcloutier.com/x86/addsd).
    """

    name = "x86.dsm.vaddsd"

name = 'x86.dsm.vaddsd' class-attribute instance-attribute

DSS_VaddpsOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Add packed single-precision floating-point elements in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_VaddpsOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Add packed single-precision floating-point elements in s1 and s2 and store the
    result in d.

    See external [documentation](https://www.felixcloutier.com/x86/addps).
    """

    name = "x86.dss.vaddps"

name = 'x86.dss.vaddps' class-attribute instance-attribute

DSS_VpxordOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Bitwise XOR of packed doubleword integers in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_VpxordOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Bitwise XOR of packed doubleword integers in s1 and s2 and store the result in d.

    See external [documentation](https://www.felixcloutier.com/x86/pxor).
    """

    name = "x86.dss.vpxord"

name = 'x86.dss.vpxord' class-attribute instance-attribute

DSS_VpxorqOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Bitwise XOR of packed quadword integers in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_VpxorqOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Bitwise XOR of packed quadword integers in s1 and s2 and store the result in d.

    See external [documentation](https://www.felixcloutier.com/x86/pxor).
    """

    name = "x86.dss.vpxorq"

name = 'x86.dss.vpxorq' class-attribute instance-attribute

DSS_VxorpdOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Bitwise XOR of packed double-precision floating-point elements in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_VxorpdOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Bitwise XOR of packed double-precision floating-point elements in s1 and s2 and
    store the result in d.

    See external [documentation](https://www.felixcloutier.com/x86/xorpd).
    """

    name = "x86.dss.vxorpd"

name = 'x86.dss.vxorpd' class-attribute instance-attribute

DSS_VxorpsOp dataclass

Bases: DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Bitwise XOR of packed single-precision floating-point elements in s1 and s2 and store the result in d.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSS_VxorpsOp(
    DSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Bitwise XOR of packed single-precision floating-point elements in s1 and s2 and
    store the result in d.

    See external [documentation](https://www.felixcloutier.com/x86/xorps).
    """

    name = "x86.dss.vxorps"

name = 'x86.dss.vxorps' class-attribute instance-attribute

DS_VmovapdOp dataclass

Bases: DS_Operation[X86VectorRegisterType, X86VectorRegisterType]

Move aligned packed double precision floating-point values from zmm1 to zmm2

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DS_VmovapdOp(DS_Operation[X86VectorRegisterType, X86VectorRegisterType]):
    """
    Move aligned packed double precision floating-point values from zmm1 to zmm2

    See external [documentation](https://www.felixcloutier.com/x86/movapd).
    """

    name = "x86.ds.vmovapd"

name = 'x86.ds.vmovapd' class-attribute instance-attribute

DSK_VmovapdOp dataclass

Bases: DSK_Operation

Move aligned packed double precision floating-point values from zmm1 to zmm2 using writemask k1

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSK_VmovapdOp(DSK_Operation):
    """
    Move aligned packed double precision floating-point values from zmm1 to zmm2 using
    writemask k1

    See external [documentation](https://www.felixcloutier.com/x86/movapd).
    """

    name = "x86.dsk.vmovapd"

name = 'x86.dsk.vmovapd' class-attribute instance-attribute

DS_VmovapsOp dataclass

Bases: DS_Operation[X86VectorRegisterType, X86VectorRegisterType]

Move aligned packed single precision floating-point values from zmm1 to zmm2

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DS_VmovapsOp(DS_Operation[X86VectorRegisterType, X86VectorRegisterType]):
    """
    Move aligned packed single precision floating-point values from zmm1 to zmm2

    See external [documentation](https://www.felixcloutier.com/x86/movaps).
    """

    name = "x86.ds.vmovaps"

name = 'x86.ds.vmovaps' class-attribute instance-attribute

MS_VmovapdOp dataclass

Bases: MS_Operation[GeneralRegisterType, X86VectorRegisterType]

Move aligned packed double precision floating-point values from zmm1 to m512

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovapdOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move aligned packed double precision floating-point values from zmm1 to m512

    See external [documentation](https://www.felixcloutier.com/x86/movapd).
    """

    name = "x86.ms.vmovapd"

name = 'x86.ms.vmovapd' class-attribute instance-attribute

MS_VmovapsOp dataclass

Bases: MS_Operation[GeneralRegisterType, X86VectorRegisterType]

Move aligned packed single precision floating-point values from zmm1 to m512

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovapsOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move aligned packed single precision floating-point values from zmm1 to m512

    See external [documentation](https://www.felixcloutier.com/x86/movaps).
    """

    name = "x86.ms.vmovaps"

name = 'x86.ms.vmovaps' class-attribute instance-attribute

MS_VmovupdOp dataclass

Bases: MS_Operation[GeneralRegisterType, X86VectorRegisterType]

Move unaligned packed double precision floating-point values from vector register to memory

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovupdOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move unaligned packed double precision floating-point values from vector register to memory

    See external [documentation](https://www.felixcloutier.com/x86/movupd).
    """

    name = "x86.ms.vmovupd"

name = 'x86.ms.vmovupd' class-attribute instance-attribute

MS_VmovupsOp dataclass

Bases: MS_Operation[GeneralRegisterType, X86VectorRegisterType]

Move unaligned packed single precision floating-point values from vector register to memory

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovupsOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move unaligned packed single precision floating-point values from vector register to memory

    See external [documentation](https://www.felixcloutier.com/x86/movups).
    """

    name = "x86.ms.vmovups"

name = 'x86.ms.vmovups' class-attribute instance-attribute

MS_VmovsdOp dataclass

Bases: MS_Operation[GeneralRegisterType, SSERegisterType]

Move a scalar double-precision floating-point value from an XMM register to memory.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovsdOp(MS_Operation[GeneralRegisterType, SSERegisterType]):
    """
    Move a scalar double-precision floating-point value from an XMM register to memory.

    See external [documentation](https://www.felixcloutier.com/x86/movsd).
    """

    name = "x86.ms.vmovsd"

name = 'x86.ms.vmovsd' class-attribute instance-attribute

DM_VmovapdOp dataclass

Bases: DM_Operation[X86VectorRegisterType, GeneralRegisterType]

Move aligned packed double precision floating-point values from memory to vector register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_VmovapdOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Move aligned packed double precision floating-point values from memory to vector
    register.

    See external [documentation](https://www.felixcloutier.com/x86/movapd).
    """

    name = "x86.dm.vmovapd"

name = 'x86.dm.vmovapd' class-attribute instance-attribute

DM_VmovapsOp dataclass

Bases: DM_Operation[X86VectorRegisterType, GeneralRegisterType]

Move aligned packed single precision floating-point values from memory to vector register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_VmovapsOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Move aligned packed single precision floating-point values from memory to vector
    register.

    See external [documentation](https://www.felixcloutier.com/x86/movaps).
    """

    name = "x86.dm.vmovaps"

name = 'x86.dm.vmovaps' class-attribute instance-attribute

DM_VmovupdOp dataclass

Bases: DM_Operation[X86VectorRegisterType, GeneralRegisterType]

Move unaligned packed double precision floating-point values from memory to vector register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_VmovupdOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Move unaligned packed double precision floating-point values from memory to vector
    register.

    See external [documentation](https://www.felixcloutier.com/x86/movupd).
    """

    name = "x86.dm.vmovupd"

name = 'x86.dm.vmovupd' class-attribute instance-attribute

DM_VmovupsOp dataclass

Bases: DM_Operation[X86VectorRegisterType, GeneralRegisterType]

Move unaligned packed single precision floating-point values from memory to vector register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_VmovupsOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Move unaligned packed single precision floating-point values from memory to vector
    register.

    See external [documentation](https://www.felixcloutier.com/x86/movups).
    """

    name = "x86.dm.vmovups"

name = 'x86.dm.vmovups' class-attribute instance-attribute

DMK_VmovapdOp dataclass

Bases: DMK_Operation[GeneralRegisterType]

Move aligned packed double precision floating-point values from memory to vector register using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DMK_VmovapdOp(DMK_Operation[GeneralRegisterType]):
    """
    Move aligned packed double precision floating-point values from memory to vector
    register using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movapd).
    """

    name = "x86.dmk.vmovapd"

name = 'x86.dmk.vmovapd' class-attribute instance-attribute

DMK_VmovupdOp dataclass

Bases: DMK_Operation[GeneralRegisterType]

Move unaligned packed double precision floating-point values from memory to vector register using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DMK_VmovupdOp(DMK_Operation[GeneralRegisterType]):
    """
    Move unaligned packed double precision floating-point values from memory to vector
    register using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movupd).
    """

    name = "x86.dmk.vmovupd"

name = 'x86.dmk.vmovupd' class-attribute instance-attribute

DMK_VmovapsOp dataclass

Bases: DMK_Operation[GeneralRegisterType]

Move aligned packed single precision floating-point values from memory to vector register using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DMK_VmovapsOp(DMK_Operation[GeneralRegisterType]):
    """
    Move aligned packed single precision floating-point values from memory to vector
    register using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movaps).
    """

    name = "x86.dmk.vmovaps"

name = 'x86.dmk.vmovaps' class-attribute instance-attribute

DMK_VmovupsOp dataclass

Bases: DMK_Operation[GeneralRegisterType]

Move unaligned packed single precision floating-point values from memory to vector register using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DMK_VmovupsOp(DMK_Operation[GeneralRegisterType]):
    """
    Move unaligned packed single precision floating-point values from memory to vector
    register using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movups).
    """

    name = "x86.dmk.vmovups"

name = 'x86.dmk.vmovups' class-attribute instance-attribute

MSK_VmovapdOp dataclass

Bases: MSK_Operation[GeneralRegisterType, X86VectorRegisterType]

Move aligned packed double precision floating-point values from vector register to memory using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MSK_VmovapdOp(MSK_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move aligned packed double precision floating-point values from vector register to
    memory using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movapd).
    """

    name = "x86.msk.vmovapd"

name = 'x86.msk.vmovapd' class-attribute instance-attribute

MSK_VmovupdOp dataclass

Bases: MSK_Operation[GeneralRegisterType, X86VectorRegisterType]

Move unaligned packed double precision floating-point values from vector register to memory using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MSK_VmovupdOp(MSK_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move unaligned packed double precision floating-point values from vector register to
    memory using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movupd).
    """

    name = "x86.msk.vmovupd"

name = 'x86.msk.vmovupd' class-attribute instance-attribute

MSK_VmovapsOp dataclass

Bases: MSK_Operation[GeneralRegisterType, X86VectorRegisterType]

Move aligned packed single precision floating-point values from vector register to memory using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MSK_VmovapsOp(MSK_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move aligned packed single precision floating-point values from vector register to
    memory using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movaps).
    """

    name = "x86.msk.vmovaps"

name = 'x86.msk.vmovaps' class-attribute instance-attribute

MSK_VmovupsOp dataclass

Bases: MSK_Operation[GeneralRegisterType, X86VectorRegisterType]

Move unaligned packed single precision floating-point values from vector register to memory using writemask k.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MSK_VmovupsOp(MSK_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Move unaligned packed single precision floating-point values from vector register to
    memory using writemask k.

    See external [documentation](https://www.felixcloutier.com/x86/movups).
    """

    name = "x86.msk.vmovups"

name = 'x86.msk.vmovups' class-attribute instance-attribute

MS_VmovntpdOp dataclass

Bases: MS_Operation[GeneralRegisterType, X86VectorRegisterType]

Moves the packed double precision floating-point values in the source operand to the destination operand using a non-temporal hint to prevent caching of the data during the write to memory.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovntpdOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Moves the packed double precision floating-point values in the source operand to the
    destination operand using a non-temporal hint to prevent caching of the data during
    the write to memory.

    See external [documentation](https://www.felixcloutier.com/x86/movntpd).
    """

    name = "x86.ms.vmovntpd"

name = 'x86.ms.vmovntpd' class-attribute instance-attribute

MS_VmovntpsOp dataclass

Bases: MS_Operation[GeneralRegisterType, X86VectorRegisterType]

Moves the packed single precision floating-point values in the source operand to the destination operand using a non-temporal hint to prevent caching of the data during the write to memory.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class MS_VmovntpsOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
    """
    Moves the packed single precision floating-point values in the source operand to the
    destination operand using a non-temporal hint to prevent caching of the data during
    the write to memory.

    See external [documentation](https://www.felixcloutier.com/x86/movntps).
    """

    name = "x86.ms.vmovntps"

name = 'x86.ms.vmovntps' class-attribute instance-attribute

DM_VbroadcastsdOp dataclass

Bases: DM_Operation[X86VectorRegisterType, GeneralRegisterType]

Broadcast low double precision floating-point element in m64 to eight locations in zmm1 using writemask k1

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_VbroadcastsdOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Broadcast low double precision floating-point element in m64 to eight locations in zmm1 using writemask k1

    See external [documentation](https://www.felixcloutier.com/x86/vbroadcast).
    """

    name = "x86.dm.vbroadcastsd"

name = 'x86.dm.vbroadcastsd' class-attribute instance-attribute

DM_VbroadcastssOp dataclass

Bases: DM_Operation[X86VectorRegisterType, GeneralRegisterType]

Broadcast single precision floating-point element to eight locations in memory

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DM_VbroadcastssOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
    """
    Broadcast single precision floating-point element to eight locations in memory

    See external [documentation](https://www.felixcloutier.com/x86/vbroadcast).
    """

    name = "x86.dm.vbroadcastss"

name = 'x86.dm.vbroadcastss' class-attribute instance-attribute

DK_KMovBOp dataclass

Bases: DK_Operation

Move 8 bits mask from source mask register to general-purpose register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DK_KMovBOp(DK_Operation):
    """
    Move 8 bits mask from source mask register to general-purpose register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.dk.kmovb"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        # kmovb uses r32 operands in assembly; convert the 64-bit register
        # index to its 32-bit name via Reg32Type.
        dest = self.destination.type
        if isinstance(dest.index, NoneAttr):
            raise ValueError("Unallocated register in assembly printing")
        dest_32 = Reg32Type.from_index(dest.index.data)
        return dest_32.register_name.data, reg(self.source)

name = 'x86.dk.kmovb' class-attribute instance-attribute

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    # kmovb uses r32 operands in assembly; convert the 64-bit register
    # index to its 32-bit name via Reg32Type.
    dest = self.destination.type
    if isinstance(dest.index, NoneAttr):
        raise ValueError("Unallocated register in assembly printing")
    dest_32 = Reg32Type.from_index(dest.index.data)
    return dest_32.register_name.data, reg(self.source)

KS_KMovBOp dataclass

Bases: KS_Operation

Move 8 bits mask from general-purpose register to destination mask register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class KS_KMovBOp(KS_Operation):
    """
    Move 8 bits mask from general-purpose register to destination mask register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.ks.kmovb"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        # kmovb uses r32 operands in assembly; convert the 64-bit register
        # index to its 32-bit name via Reg32Type.
        source = self.source.type
        assert isinstance(source, GeneralRegisterType)
        if isinstance(source.index, NoneAttr):
            raise ValueError("Unallocated register in assembly printing")
        source_32 = Reg32Type.from_index(source.index.data)
        return reg(self.destination), source_32.register_name.data

name = 'x86.ks.kmovb' class-attribute instance-attribute

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    # kmovb uses r32 operands in assembly; convert the 64-bit register
    # index to its 32-bit name via Reg32Type.
    source = self.source.type
    assert isinstance(source, GeneralRegisterType)
    if isinstance(source.index, NoneAttr):
        raise ValueError("Unallocated register in assembly printing")
    source_32 = Reg32Type.from_index(source.index.data)
    return reg(self.destination), source_32.register_name.data

DK_KMovWOp dataclass

Bases: DK_Operation

Move 16 bits mask from source mask register to general-purpose register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DK_KMovWOp(DK_Operation):
    """
    Move 16 bits mask from source mask register to general-purpose register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.dk.kmovw"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        # kmovw uses r32 operands in assembly; convert the 64-bit register
        # index to its 32-bit name via Reg32Type.
        dest = self.destination.type
        if isinstance(dest.index, NoneAttr):
            raise ValueError("Unallocated register in assembly printing")
        dest_32 = Reg32Type.from_index(dest.index.data)
        return dest_32.register_name.data, reg(self.source)

name = 'x86.dk.kmovw' class-attribute instance-attribute

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    # kmovw uses r32 operands in assembly; convert the 64-bit register
    # index to its 32-bit name via Reg32Type.
    dest = self.destination.type
    if isinstance(dest.index, NoneAttr):
        raise ValueError("Unallocated register in assembly printing")
    dest_32 = Reg32Type.from_index(dest.index.data)
    return dest_32.register_name.data, reg(self.source)

KS_KMovWOp dataclass

Bases: KS_Operation

Move 16 bits mask from general-purpose register to destination mask register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class KS_KMovWOp(KS_Operation):
    """
    Move 16 bits mask from general-purpose register to destination mask register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.ks.kmovw"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        # kmovw uses r32 operands in assembly; convert the 64-bit register
        # index to its 32-bit name via Reg32Type.
        source = self.source.type
        assert isinstance(source, GeneralRegisterType)
        if isinstance(source.index, NoneAttr):
            raise ValueError("Unallocated register in assembly printing")
        source_32 = Reg32Type.from_index(source.index.data)
        return reg(self.destination), source_32.register_name.data

name = 'x86.ks.kmovw' class-attribute instance-attribute

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    # kmovw uses r32 operands in assembly; convert the 64-bit register
    # index to its 32-bit name via Reg32Type.
    source = self.source.type
    assert isinstance(source, GeneralRegisterType)
    if isinstance(source.index, NoneAttr):
        raise ValueError("Unallocated register in assembly printing")
    source_32 = Reg32Type.from_index(source.index.data)
    return reg(self.destination), source_32.register_name.data

DK_KMovDOp dataclass

Bases: DK_Operation

Move 32 bits mask from source mask register to general-purpose register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DK_KMovDOp(DK_Operation):
    """
    Move 32 bits mask from source mask register to general-purpose register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.dk.kmovd"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        # kmovd uses r32 operands in assembly; convert the 64-bit register
        # index to its 32-bit name via Reg32Type.
        dest = self.destination.type
        if isinstance(dest.index, NoneAttr):
            raise ValueError("Unallocated register in assembly printing")
        dest_32 = Reg32Type.from_index(dest.index.data)
        return dest_32.register_name.data, reg(self.source)

name = 'x86.dk.kmovd' class-attribute instance-attribute

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    # kmovd uses r32 operands in assembly; convert the 64-bit register
    # index to its 32-bit name via Reg32Type.
    dest = self.destination.type
    if isinstance(dest.index, NoneAttr):
        raise ValueError("Unallocated register in assembly printing")
    dest_32 = Reg32Type.from_index(dest.index.data)
    return dest_32.register_name.data, reg(self.source)

KS_KMovDOp dataclass

Bases: KS_Operation

Move 32 bits mask from general-purpose register to destination mask register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class KS_KMovDOp(KS_Operation):
    """
    Move 32 bits mask from general-purpose register to destination mask register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.ks.kmovd"

    def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
        # kmovd uses r32 operands in assembly; convert the 64-bit register
        # index to its 32-bit name via Reg32Type.
        source = self.source.type
        assert isinstance(source, GeneralRegisterType)
        if isinstance(source.index, NoneAttr):
            raise ValueError("Unallocated register in assembly printing")
        source_32 = Reg32Type.from_index(source.index.data)
        return reg(self.destination), source_32.register_name.data

name = 'x86.ks.kmovd' class-attribute instance-attribute

assembly_line_args() -> tuple[AssemblyInstructionArg | None, ...]

Source code in xdsl/dialects/x86/ops.py

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
    # kmovd uses r32 operands in assembly; convert the 64-bit register
    # index to its 32-bit name via Reg32Type.
    source = self.source.type
    assert isinstance(source, GeneralRegisterType)
    if isinstance(source.index, NoneAttr):
        raise ValueError("Unallocated register in assembly printing")
    source_32 = Reg32Type.from_index(source.index.data)
    return reg(self.destination), source_32.register_name.data

DK_KMovQOp dataclass

Bases: DK_Operation

Move 64 bits mask from source mask register to general-purpose register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DK_KMovQOp(DK_Operation):
    """
    Move 64 bits mask from source mask register to general-purpose register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.dk.kmovq"

name = 'x86.dk.kmovq' class-attribute instance-attribute

KS_KMovQOp dataclass

Bases: KS_Operation

Move 64 bits mask from general-purpose register to destination mask register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class KS_KMovQOp(KS_Operation):
    """
    Move 64 bits mask from general-purpose register to destination mask register.

    See external [documentation](https://www.felixcloutier.com/x86/kmovw:kmovb:kmovq:kmovd).
    """

    name = "x86.ks.kmovq"

name = 'x86.ks.kmovq' class-attribute instance-attribute

DSI_Vextractf64x4Op dataclass

Bases: DSI8_Operation[AVX2RegisterType, AVX512RegisterType]

Extract 256 bits of packed double-precision floating-point elements from a ZMM register into a YMM register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSI_Vextractf64x4Op(DSI8_Operation[AVX2RegisterType, AVX512RegisterType]):
    """
    Extract 256 bits of packed double-precision floating-point elements from a ZMM
    register into a YMM register.

    See external [documentation](https://www.felixcloutier.com/x86/vextractf128:vextractf32x4:vextractf64x2:vextractf32x8:vextractf64x4).
    """

    name = "x86.dsi.vextractf64x4"

name = 'x86.dsi.vextractf64x4' class-attribute instance-attribute

DSI_Vextractf128Op dataclass

Bases: DSI8_Operation[SSERegisterType, AVX2RegisterType]

Extract 128 bits of packed floating-point elements from a YMM register into an XMM register.

See external documentation.

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSI_Vextractf128Op(DSI8_Operation[SSERegisterType, AVX2RegisterType]):
    """
    Extract 128 bits of packed floating-point elements from a YMM register into an XMM
    register.

    See external [documentation](https://www.felixcloutier.com/x86/vextractf128:vextractf32x4:vextractf64x2:vextractf32x8:vextractf64x4).
    """

    name = "x86.dsi.vextractf128"

name = 'x86.dsi.vextractf128' class-attribute instance-attribute

DSSI_ShufpsOp dataclass

Bases: DSSI_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]

Selects a single precision floating-point value of an input quadruplet using a two-bit control and move to a designated element of the destination operand. Each 64-bit element-pair of a 128-bit lane of the destination operand is interleaved between the corresponding lane of the first source operand and the second source operand at the granularity 128 bits. Each two bits in the imm8 byte, starting from bit 0, is the select control of the corresponding element of a 128-bit lane of the destination to received the shuffled result of an input quadruplet. The two lower elements of a 128-bit lane in the destination receives shuffle results from the quadruple of the first source operand. The next two elements of the destination receives shuffle results from the quadruple of the second source operand.

See external documentation

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class DSSI_ShufpsOp(
    DSSI_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
):
    """
    Selects a single precision floating-point value of an input quadruplet using a
    two-bit control and move to a designated element of the destination operand.
    Each 64-bit element-pair of a 128-bit lane of the destination operand is interleaved
    between the corresponding lane of the first source operand and the second source
    operand at the granularity 128 bits. Each two bits in the imm8 byte, starting from
    bit 0, is the select control of the corresponding element of a 128-bit lane of the
    destination to received the shuffled result of an input quadruplet. The two lower
    elements of a 128-bit lane in the destination receives shuffle results from the
    quadruple of the first source operand. The next two elements of the destination
    receives shuffle results from the quadruple of the second source operand.

    See external [documentation](https://www.felixcloutier.com/x86/shufps)
    """

    name = "x86.dssi.shufps"

name = 'x86.dssi.shufps' class-attribute instance-attribute

GetAnyRegisterOperation

Bases: X86AsmOperation, X86HasRegisterConstraints, ABC, Generic[R1InvT]

This instruction allows us to create an SSAValue for a given register name.

Source code in xdsl/dialects/x86/ops.py

class GetAnyRegisterOperation(
    X86AsmOperation,
    X86HasRegisterConstraints,
    ABC,
    Generic[R1InvT],
):
    """
    This instruction allows us to create an SSAValue for a given register name.
    """

    result: OpResult[R1InvT] = result_def(R1InvT)

    assembly_format = "attr-dict `:` type($result)"

    traits = traits_def(NoMemoryEffect())

    def __init__(
        self,
        register_type: R1InvT,
    ):
        super().__init__(result_types=[register_type])

    def assembly_line(self) -> str | None:
        return None

result: OpResult[R1InvT] = result_def(R1InvT) class-attribute instance-attribute

assembly_format = 'attr-dict `:` type($result)' class-attribute instance-attribute

traits = traits_def(NoMemoryEffect()) class-attribute instance-attribute

__init__(register_type: R1InvT)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    register_type: R1InvT,
):
    super().__init__(result_types=[register_type])

assembly_line() -> str | None

Source code in xdsl/dialects/x86/ops.py

def assembly_line(self) -> str | None:
    return None

GetRegisterOp dataclass

Bases: GetAnyRegisterOperation[GeneralRegisterType]

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class GetRegisterOp(GetAnyRegisterOperation[GeneralRegisterType]):
    name = "x86.get_register"

name = 'x86.get_register' class-attribute instance-attribute

GetAVXRegisterOp dataclass

Bases: GetAnyRegisterOperation[X86VectorRegisterType]

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class GetAVXRegisterOp(GetAnyRegisterOperation[X86VectorRegisterType]):
    name = "x86.get_avx_register"

name = 'x86.get_avx_register' class-attribute instance-attribute

GetMaskRegisterOp dataclass

Bases: GetAnyRegisterOperation[AVX512MaskRegisterType]

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class GetMaskRegisterOp(GetAnyRegisterOperation[AVX512MaskRegisterType]):
    name = "x86.get_mask_register"

name = 'x86.get_mask_register' class-attribute instance-attribute

ParallelMovOp

Bases: X86HasRegisterConstraints

Source code in xdsl/dialects/x86/ops.py

@irdl_op_definition
class ParallelMovOp(X86HasRegisterConstraints):
    name = "x86.parallel_mov"
    inputs = var_operand_def(X86RegisterType)
    outputs: VarOpResult[X86RegisterType] = var_result_def(X86RegisterType)
    free_registers = opt_prop_def(ArrayAttr[X86RegisterType])

    assembly_format = "$inputs attr-dict `:` functional-type($inputs, $outputs)"
    irdl_options = (ParsePropInAttrDict(),)

    traits = traits_def(RegisterAllocatedMemoryEffect())

    def __init__(
        self,
        inputs: Sequence[SSAValue],
        outputs: Sequence[X86RegisterType],
        free_registers: ArrayAttr[X86RegisterType] | None = None,
    ):
        super().__init__(
            operands=(inputs,),
            result_types=(outputs,),
            properties={"free_registers": free_registers},
        )

    def verify_(self) -> None:
        if len(self.inputs) != len(self.outputs):
            raise VerifyException(
                "Input count must match output count. "
                f"Num inputs: {len(self.inputs)}, Num outputs: {len(self.outputs)}"
            )

        input_types = cast(Sequence[X86RegisterType], self.inputs.types)
        output_types = cast(Sequence[X86RegisterType], self.outputs.types)

        # Check type of register type matches for input and output
        for input_type, output_type in zip(input_types, output_types, strict=True):
            if type(input_type) is not type(output_type):
                raise VerifyException("Input type must match output type.")

        # Check outputs are distinct if allocated
        filtered_outputs = tuple(i for i in output_types if i.is_allocated)
        if len(filtered_outputs) != len(set(filtered_outputs)):
            raise VerifyException("Outputs must be unallocated or distinct.")

name = 'x86.parallel_mov' class-attribute instance-attribute

inputs = var_operand_def(X86RegisterType) class-attribute instance-attribute

outputs: VarOpResult[X86RegisterType] = var_result_def(X86RegisterType) class-attribute instance-attribute

free_registers = opt_prop_def(ArrayAttr[X86RegisterType]) class-attribute instance-attribute

assembly_format = '$inputs attr-dict `:` functional-type($inputs, $outputs)' class-attribute instance-attribute

irdl_options = (ParsePropInAttrDict(),) class-attribute instance-attribute

traits = traits_def(RegisterAllocatedMemoryEffect()) class-attribute instance-attribute

__init__(inputs: Sequence[SSAValue], outputs: Sequence[X86RegisterType], free_registers: ArrayAttr[X86RegisterType] | None = None)

Source code in xdsl/dialects/x86/ops.py

def __init__(
    self,
    inputs: Sequence[SSAValue],
    outputs: Sequence[X86RegisterType],
    free_registers: ArrayAttr[X86RegisterType] | None = None,
):
    super().__init__(
        operands=(inputs,),
        result_types=(outputs,),
        properties={"free_registers": free_registers},
    )

verify_() -> None

Source code in xdsl/dialects/x86/ops.py

def verify_(self) -> None:
    if len(self.inputs) != len(self.outputs):
        raise VerifyException(
            "Input count must match output count. "
            f"Num inputs: {len(self.inputs)}, Num outputs: {len(self.outputs)}"
        )

    input_types = cast(Sequence[X86RegisterType], self.inputs.types)
    output_types = cast(Sequence[X86RegisterType], self.outputs.types)

    # Check type of register type matches for input and output
    for input_type, output_type in zip(input_types, output_types, strict=True):
        if type(input_type) is not type(output_type):
            raise VerifyException("Input type must match output type.")

    # Check outputs are distinct if allocated
    filtered_outputs = tuple(i for i in output_types if i.is_allocated)
    if len(filtered_outputs) != len(set(filtered_outputs)):
        raise VerifyException("Outputs must be unallocated or distinct.")

X86AsmTarget dataclass

Bases: Target

Source code in xdsl/dialects/x86/ops.py

@dataclass(frozen=True)
class X86AsmTarget(Target):
    name = "x86-asm"

    def emit(self, ctx: Context, module: ModuleOp, output: IO[str]) -> None:
        print_assembly(module, output)

name = 'x86-asm' class-attribute instance-attribute

__init__() -> None

emit(ctx: Context, module: ModuleOp, output: IO[str]) -> None

Source code in xdsl/dialects/x86/ops.py

def emit(self, ctx: Context, module: ModuleOp, output: IO[str]) -> None:
    print_assembly(module, output)

print_assembly(module: ModuleOp, output: IO[str]) -> None

Source code in xdsl/dialects/x86/ops.py

def print_assembly(module: ModuleOp, output: IO[str]) -> None:
    printer = AssemblyPrinter(stream=output)
    print(".intel_syntax noprefix", file=output)
    printer.print_module(module)

x86_code(module: ModuleOp) -> str

Source code in xdsl/dialects/x86/ops.py

def x86_code(module: ModuleOp) -> str:
    stream = StringIO()
    print_assembly(module, stream)
    return stream.getvalue()