Registers
registers
¶
X86_GPR_POOL_KEY = 'x86.reg'
module-attribute
¶
Pool key for x86 general-purpose register allocation.
64-bit, 32-bit, 16-bit, and 8-bit names share one physical register per index (e.g.
rax / eax / ax / al). Indices are drawn from a single pool; see concrete
subclasses of [xdsl.dialects.x86.GeneralRegisterType].
X86_INDEX_BY_NAME = {'rax': 0, 'rcx': 1, 'rdx': 2, 'rbx': 3, 'rsp': 4, 'rbp': 5, 'rsi': 6, 'rdi': 7, 'r8': 8, 'r9': 9, 'r10': 10, 'r11': 11, 'r12': 12, 'r13': 13, 'r14': 14, 'r15': 15}
module-attribute
¶
Mapping of x86 64-bit register names to their indices.
See external documentation.
REG32_INDEX_BY_NAME = {'eax': 0, 'ecx': 1, 'edx': 2, 'ebx': 3, 'esp': 4, 'ebp': 5, 'esi': 6, 'edi': 7, 'r8d': 8, 'r9d': 9, 'r10d': 10, 'r11d': 11, 'r12d': 12, 'r13d': 13, 'r14d': 14, 'r15d': 15}
module-attribute
¶
REG16_INDEX_BY_NAME = {'ax': 0, 'cx': 1, 'dx': 2, 'bx': 3, 'sp': 4, 'bp': 5, 'si': 6, 'di': 7, 'r8w': 8, 'r9w': 9, 'r10w': 10, 'r11w': 11, 'r12w': 12, 'r13w': 13, 'r14w': 14, 'r15w': 15}
module-attribute
¶
REG8_INDEX_BY_NAME = {'al': 0, 'cl': 1, 'dl': 2, 'bl': 3, 'spl': 4, 'bpl': 5, 'sil': 6, 'dil': 7, 'r8b': 8, 'r9b': 9, 'r10b': 10, 'r11b': 11, 'r12b': 12, 'r13b': 13, 'r14b': 14, 'r15b': 15}
module-attribute
¶
Low-byte 8-bit names only; ah/ch/dh/bh are not modeled (see
:class:Reg8Type).
UNALLOCATED_REG64 = Reg64Type.unallocated()
module-attribute
¶
UNALLOCATED_REG32 = Reg32Type.unallocated()
module-attribute
¶
UNALLOCATED_REG16 = Reg16Type.unallocated()
module-attribute
¶
UNALLOCATED_REG8 = Reg8Type.unallocated()
module-attribute
¶
RAX = Reg64Type.from_name('rax')
module-attribute
¶
RCX = Reg64Type.from_name('rcx')
module-attribute
¶
RDX = Reg64Type.from_name('rdx')
module-attribute
¶
RBX = Reg64Type.from_name('rbx')
module-attribute
¶
RSP = Reg64Type.from_name('rsp')
module-attribute
¶
RBP = Reg64Type.from_name('rbp')
module-attribute
¶
RSI = Reg64Type.from_name('rsi')
module-attribute
¶
RDI = Reg64Type.from_name('rdi')
module-attribute
¶
R8 = Reg64Type.from_name('r8')
module-attribute
¶
R9 = Reg64Type.from_name('r9')
module-attribute
¶
R10 = Reg64Type.from_name('r10')
module-attribute
¶
R11 = Reg64Type.from_name('r11')
module-attribute
¶
R12 = Reg64Type.from_name('r12')
module-attribute
¶
R13 = Reg64Type.from_name('r13')
module-attribute
¶
R14 = Reg64Type.from_name('r14')
module-attribute
¶
R15 = Reg64Type.from_name('r15')
module-attribute
¶
EAX = Reg32Type.from_name('eax')
module-attribute
¶
ECX = Reg32Type.from_name('ecx')
module-attribute
¶
EDX = Reg32Type.from_name('edx')
module-attribute
¶
EBX = Reg32Type.from_name('ebx')
module-attribute
¶
ESP = Reg32Type.from_name('esp')
module-attribute
¶
EBP = Reg32Type.from_name('ebp')
module-attribute
¶
ESI = Reg32Type.from_name('esi')
module-attribute
¶
EDI = Reg32Type.from_name('edi')
module-attribute
¶
R8D = Reg32Type.from_name('r8d')
module-attribute
¶
R9D = Reg32Type.from_name('r9d')
module-attribute
¶
R10D = Reg32Type.from_name('r10d')
module-attribute
¶
R11D = Reg32Type.from_name('r11d')
module-attribute
¶
R12D = Reg32Type.from_name('r12d')
module-attribute
¶
R13D = Reg32Type.from_name('r13d')
module-attribute
¶
R14D = Reg32Type.from_name('r14d')
module-attribute
¶
R15D = Reg32Type.from_name('r15d')
module-attribute
¶
AX = Reg16Type.from_name('ax')
module-attribute
¶
CX = Reg16Type.from_name('cx')
module-attribute
¶
DX = Reg16Type.from_name('dx')
module-attribute
¶
BX = Reg16Type.from_name('bx')
module-attribute
¶
SP = Reg16Type.from_name('sp')
module-attribute
¶
BP = Reg16Type.from_name('bp')
module-attribute
¶
SI = Reg16Type.from_name('si')
module-attribute
¶
DI = Reg16Type.from_name('di')
module-attribute
¶
R8W = Reg16Type.from_name('r8w')
module-attribute
¶
R9W = Reg16Type.from_name('r9w')
module-attribute
¶
R10W = Reg16Type.from_name('r10w')
module-attribute
¶
R11W = Reg16Type.from_name('r11w')
module-attribute
¶
R12W = Reg16Type.from_name('r12w')
module-attribute
¶
R13W = Reg16Type.from_name('r13w')
module-attribute
¶
R14W = Reg16Type.from_name('r14w')
module-attribute
¶
R15W = Reg16Type.from_name('r15w')
module-attribute
¶
AL = Reg8Type.from_name('al')
module-attribute
¶
CL = Reg8Type.from_name('cl')
module-attribute
¶
DL = Reg8Type.from_name('dl')
module-attribute
¶
BL = Reg8Type.from_name('bl')
module-attribute
¶
SPL = Reg8Type.from_name('spl')
module-attribute
¶
BPL = Reg8Type.from_name('bpl')
module-attribute
¶
SIL = Reg8Type.from_name('sil')
module-attribute
¶
DIL = Reg8Type.from_name('dil')
module-attribute
¶
R8B = Reg8Type.from_name('r8b')
module-attribute
¶
R9B = Reg8Type.from_name('r9b')
module-attribute
¶
R10B = Reg8Type.from_name('r10b')
module-attribute
¶
R11B = Reg8Type.from_name('r11b')
module-attribute
¶
R12B = Reg8Type.from_name('r12b')
module-attribute
¶
R13B = Reg8Type.from_name('r13b')
module-attribute
¶
R14B = Reg8Type.from_name('r14b')
module-attribute
¶
R15B = Reg8Type.from_name('r15b')
module-attribute
¶
RFLAGS_INDEX_BY_NAME = {'rflags': 0}
module-attribute
¶
UNALLOCATED_RFLAGS = RFLAGSRegisterType.unallocated()
module-attribute
¶
RFLAGS = RFLAGSRegisterType.from_name('rflags')
module-attribute
¶
X86_VECTOR_POOL_KEY = 'x86.vector'
module-attribute
¶
Pool key for x86 vector register allocation.
xmm*, ymm*, and zmm* share one physical register per index where they
overlap (e.g. xmm0/ymm0/zmm0). Indices are drawn from a single pool; targets configure
how many names exist (e.g. 8, 16, or 32) via
RegisterType.allocatable_registers.
SSE_INDEX_BY_NAME = {f'xmm{i}': i for i in range(32)}
module-attribute
¶
Mapping of SSE register names to their indices.
See external # documentation.
UNALLOCATED_SSE = SSERegisterType.unallocated()
module-attribute
¶
XMM = tuple(SSERegisterType.from_name(f'xmm{i}') for i in range(32))
module-attribute
¶
AVX2_INDEX_BY_NAME = {f'ymm{i}': i for i in range(32)}
module-attribute
¶
Mapping of AVX2 register names to their indices.
See external # documentation.
UNALLOCATED_AVX2 = AVX2RegisterType.unallocated()
module-attribute
¶
YMM = tuple(AVX2RegisterType.from_name(f'ymm{i}') for i in range(32))
module-attribute
¶
X86AVX512_INDEX_BY_NAME = {f'zmm{i}': i for i in range(32)}
module-attribute
¶
Mapping of AVX512 register names to their indices.
See external # documentation.
UNALLOCATED_AVX512 = AVX512RegisterType.unallocated()
module-attribute
¶
ZMM = tuple(AVX512RegisterType.from_name(f'zmm{i}') for i in range(32))
module-attribute
¶
X86AVX512_MASK_INDEX_BY_NAME = {f'k{i}': i for i in range(8)}
module-attribute
¶
UNALLOCATED_AVX512_MASK = AVX512MaskRegisterType.unallocated()
module-attribute
¶
K = tuple(AVX512MaskRegisterType.from_name(f'k{i}') for i in range(8))
module-attribute
¶
X86RegisterType
dataclass
¶
Bases: RegisterType, ABC
The abstract class for all x86 register types.
Source code in xdsl/dialects/x86/registers.py
GeneralRegisterType
dataclass
¶
Bases: X86RegisterType, ABC
Abstract base for x86 scalar general-purpose register types (64/32/16/8-bit names).
Concrete subclasses set the assembly name width; all share :data:X86_GPR_POOL_KEY
for register allocation.
Source code in xdsl/dialects/x86/registers.py
register_pool_key() -> str
classmethod
¶
allocatable_registers()
classmethod
¶
Registers of this type that can be used for register allocation.
Returns a tuple of GeneralRegisterType instances corresponding to registers that are allocatable according to the x86-64 System V ABI. This excludes registers with special purposes (e.g., stack pointer, base pointer).
Source code in xdsl/dialects/x86/registers.py
Reg64Type
dataclass
¶
Bases: GeneralRegisterType
64-bit x86 general-purpose register names (rax, r8, …).
Source code in xdsl/dialects/x86/registers.py
Reg32Type
dataclass
¶
Bases: GeneralRegisterType
32-bit x86 general-purpose register names (eax, r8d, …).
Source code in xdsl/dialects/x86/registers.py
Reg16Type
dataclass
¶
Bases: GeneralRegisterType
16-bit x86 general-purpose register names (ax, r8w, …).
Source code in xdsl/dialects/x86/registers.py
Reg8Type
dataclass
¶
Bases: GeneralRegisterType
8-bit x86 low-byte register names (al, r8b, …).
High-byte names ah/ch/dh/bh are not represented: they share indices
with low bytes but :class:~xdsl.backend.register_type.RegisterType assumes one
canonical name per pool index.
Source code in xdsl/dialects/x86/registers.py
RFLAGSRegisterType
dataclass
¶
Bases: X86RegisterType
A scalar x86 register type representing the RFLAGS register.
Source code in xdsl/dialects/x86/registers.py
X86VectorRegisterType
dataclass
¶
Bases: X86RegisterType, ABC
The abstract class for all x86 vector register types.
Source code in xdsl/dialects/x86/registers.py
register_pool_key() -> str
classmethod
¶
SSERegisterType
dataclass
¶
Bases: X86VectorRegisterType
An x86 register type for SSE instructions.
Source code in xdsl/dialects/x86/registers.py
AVX2RegisterType
dataclass
¶
Bases: X86VectorRegisterType
An x86 register type for AVX2 instructions.
Source code in xdsl/dialects/x86/registers.py
AVX512RegisterType
dataclass
¶
Bases: X86VectorRegisterType
An x86 register type for AVX512 instructions.
Source code in xdsl/dialects/x86/registers.py
AVX512MaskRegisterType
dataclass
¶
Bases: X86RegisterType
An x86 mask register type for AVX512 instructions.