Rv32
rv32
RISC-V 32-bit (RV32) dialect operations and types.
This module defines the RV32-specific variant of RISC-V operations, using 5-bit immediates for 32-bit architectures.
RV32 = Dialect('rv32', [LiOp, GetRegisterOp], [])
module-attribute
LiOp
Bases: LiOperation[I32]
Loads a 32-bit immediate into rd.
This is an assembler pseudo-instruction.
See external documentation.
Source code in xdsl/dialects/rv32.py
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 | |
name = 'rv32.li'
class-attribute
instance-attribute
__init__(immediate: int | IntegerAttr[I32] | str | LabelAttr, *, rd: IntRegisterType = Registers.UNALLOCATED_INT, comment: str | StringAttr | None = None)
Source code in xdsl/dialects/rv32.py
40 41 42 43 44 45 46 47 48 49 | |
custom_parse_attributes(parser: Parser) -> dict[str, Attribute]
classmethod
Source code in xdsl/dialects/rv32.py
51 52 53 54 55 | |
GetRegisterOp
dataclass
Bases: GetAnyRegisterOperation[IntRegisterType]
Source code in xdsl/dialects/rv32.py
58 59 60 | |